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DP83256 Datasheet(PDF) 12 Page - National Semiconductor (TI) |
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DP83256 Datasheet(HTML) 12 Page - National Semiconductor (TI) |
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12 / 144 page  30 Functional Description (Continued) 33 TRANSMITTER BLOCK The Transmitter Block accepts 10-bit bytes consisting of 8 bits data 1 bit parity and 1 bit control information from the Configuration Switch The Transmitter Block performs the following operations Encodes the data from 4B to 5B coding Filters out code violations from the data stream Is capable of generating Idle Master Halt Quiet or oth- er user defined symbol pairs Converts the data stream from NRZ to NRZI for trans- mission Serializes data During normal operation the Transmitter Block presents se- rial data to a PMD transmitter While in Internal Loopback mode the Transmitter Block presents serial data to the Receiver Block While in the Ex- ternal Loopback mode the Transmitter Block presents seri- al data to the Clock Recovery Module The Transmitter Block consists of the following functional blocks Data Registers Parity Checker 4B5B Encoder Repeat Filter Smoother Line State Generator Injection Control Logic Shift Register NRZ to NRZI Encoder See Figure 3-3 Transmitter Block Diagram TLF11708 – 5 FIGURE 3-3 Transmitter Block Diagram 12 |
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