DP83256 datasheet(11/144 Pages) NSC

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30 Functional Description (Continued)

Super Idle Line State

The Line State Detector recognizes the incoming data to be

in the Super Idle Line State upon the reception of 8 consec-

utive Idle symbol pairs nominally (plus 1 symbol pair)

The Super Idle Line State is used to insure synchronization

of PCM signalling

No Signal Detect

The Line State Detector recognizes the incoming data to be

in the No Signal Detect state upon the deassertion of the

Signal Detect signal or lack of internal clock detect from the

Clock Recovery Module and reception of 8 Quiet symbol

pairs nominally No Signal Detect indicates that the incom-

ing link is inactive This is the same as receiving Quiet Line

State (QLS)

Master Line State

The Line State Detector recognizes the incoming data to be

in the Master Line State upon the reception of eight consec-

utive Halt-Quiet symbol pairs nominally (plus up to 2 symbol

pairs in start up cases)

The Master Line State is used in the handshaking sequence

of the PHY Connection Management process

Halt Line State

The Line State Detector recognizes the incoming data to be

in the Halt Line State upon the reception of eight consecu-

tive Halt symbol pairs nominally (plus up to 2 symbol pairs in

start up cases)

The Halt Line State is used in the handshaking sequence of

the PHY Connection Management process

Quiet Line State

The Line State Detector recognizes the incoming data to be

in the Quiet Line State upon the reception of eight consecu-

tive Quiet symbol pairs nominally (plus up to 9 bits of 0 in

start up cases)

The Quiet Line State is used in the handshaking sequence

of the PHY Connection Management process

Noise Line State

The Line State Detector recognizes the incoming data to be

in the Noise Line State upon the reception of 16 noise sym-

bol pairs without entering any known line state

The Noise Line State indicates that data is not being re-

ceived correctly

Line State Unknown

The Line State Detector recognizes the incoming data to be

in the Line State Unknown state upon the reception of 1

inconsistent symbol pair (ie data that is not expected) This

may signify the beginning of a new line state

Line State Unknown indicates that data is not being re-

ceived correctly If the condition persists the Noise Line

State (NLS) may be entered

ELASTICITY BUFFER

The Elasticity Buffer performs the function of a ‘‘variable

depth’’ FIFO to compensate for phase and frequency clock

skews between the Receive Clock (RXCg) and the Local

Byte Clock (LBC)

Bit 5 (EBOU) of the Receive Condition Register B (RCRB) is

set to 1 to indicate an error condition when the Elasticity

Buffer cannot compensate for the clock skew

The Elasticity Buffer will support a maximum clock skew of

50 ppm with a maximum packet length of 4500 bytes

To make up for the accumulation of frequency disparity be-

tween the two clocks the Elasticity Buffer will insert or de-

lete Idle symbol pairs in the preamble Data is written into

the byte-wide registers of the Elasticity Buffer with the Re-

ceive Clock while data is read from the registers with the

Local Byte Clock

The Elasticity Buffer will recenter (ie set the read and write

pointers to a predetermined distance from each other) upon

the detection of a JK or every four byte times during PHY

Invalid (ie MLS HLS QLS NLS NSD) and Idle Line State

The Elasticity Buffer is designed such that a given register

cannot be written and read simultaneously under normal op-

erating conditions To avoid metastability problems the EB

overflow event is flagged and the data is tagged before the

overunder run actually occurs

LINK ERROR DETECTOR

The Link Error Detector provides continuous monitoring of

an active link (ie during Active and Idle Line States) to

insure that it does not exceed the maximum Bit Error Rate

requirement as set by the ANSI standard for a station to

remain on the ring

Upon detecting a link error the internal 8-bit Link Error Mon-

itor Counter is decremented The start value for the Link

Error Monitor Counter is programmed through the Link Error

Threshold Register (LETR) When the Link Error Monitor

Counter reaches zero bit 4 (LEMT) of the Interrupt Condi-

tion Register (ICR) is set to 1 The current value of the Link

Error Monitor Counter can be read through the Current Link

Error Count Register (CLECR) For higher error rates the

current value is an approximate count because the counter

rolls over

There are two ways to monitor Link Error Rate polling and

interrupt

Polling

The Link Error Monitor Counter can be set to a large value

like FF This will allow for the greatest time between polling

the register This start value is programmed through the Link

Error Threshold Register (LETR)

Upon detecting a link error the Line Error Monitor Counter

is decremented

The Host System reads the current value of the Link Error

Monitor Counter via the Current Link Error Count Register

(CLECR) The Counter is then reset to FF

Interrupt

The Link Error Monitor Counter can be set to a small value

like 5 to 10 This start value is programmed through the Link

Error Threshold Register (LETR)

Upon detecting a link error the Line Error Monitor Counter

is decremented When the counter reaches zero bit 4

(LEMT) of the Interrupt Condition Register (ICR) is set to 1

and the interrupt signal goes low interrupting the Host Sys-

tem

Miscellaneous Items

When bit 0 (RUN) of the Mode Register (MR) is set to zero

or when the PLAYERa device is reset through the Reset

pin (ERST) the internal signal detect line is internally

forced to zero and the Line State Detector is set to Line

State Unknown and No Signal Detect

DP83256 Datasheet(PDF) 11 Page - National Semiconductor (TI)

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