DP83256 datasheet(71/144 Pages) NSC

71 / 144 page

50 Registers (Continued)

527 INTERRUPT CONDITION COMPARISON REGISTER (ICCR)

The Interrupt Condition Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYERa

device before it can be written to by the Control Bus Interface

The current state of the Interrupt Condition Register (ICR) is automatically written into the Interrupt Condition Comparison

During a Control Bus Interface write cycle the PLAYERa device will set the Conditional Write Inhibit bit (CWI) of the Interrupt

Condition Register (ICR) to 1 and disallow the setting or clearing of a bit within ICR when the value of a bit in ICR differs from the

value of the corresponding bit in the interrupt Condition Comparison Register

ACCESS RULES

ADDRESS

READ

WRITE

1Ah

Always

UDIC

RCBC

RCAC

LEMTC

CWIC

CCRC

CPEC

DPEC

Bit

Symbol

Description

DPEC

PHY

REQUEST DATA PARITY ERROR COMPARISON

The comparison bit for the PHY

Request Data Parity

Error bit (DPE) of the Interrupt Condition Register (ICR)

CPEC

CONTROL BUS DATA PARITY ERROR COMPARISON

The comparison bit for the Control Bus Data Parity Error

bit (CPE) of the Interrupt Condition Register (ICR)

CCRC

CONTROL BUS WRITE COMMAND REJECT COMPARISON

The comparison bit for the Control Bus Write

Command Reject bit (CCR) of the Interrupt Condition Register (ICR)

CWIC

CONDITIONAL WRITE INHIBIT COMPARISON

The comparison bit for the Conditional Write Inhibit bit (CWI) of

the Interrupt Condition Register (ICR)

LEMTC

LINK ERROR MONITOR THRESHOLD COMPARISON

The comparison bit for the Link Error Monitor Threshold

bit (LEMT) of the Interrupt Condition Register (ICR)

RCAC

RECEIVE CONDITION A COMPARISON

The comparison bit for the Receive Condition A bit (RCA) of the

Interrupt Condition Register (ICR)

RCBC

RECEIVE CONDITION B COMPARISON

The comparison bit for the Receive Condition B bit (RCB) of the

Interrupt Condition Register (ICR)

UDIC

USER DEFINABLE INTERRUPT COMPARISON

The comparison bit for the User Definable Interrupt bit (UDIC) of

the Interrupt Condition Register (ICR)

DP83256 Datasheet(PDF) 71 Page - National Semiconductor (TI)

DP83256 Datasheet(HTML) 71 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL