DP83256 datasheet(87/144 Pages) NSC

87 / 144 page

50 Registers (Continued)

543 GAIN REGISTER (GAINREG)

The Gain Register contains the settings for the CGM’s on-chip programmable loop filter For optimal jitter performance on the

revision A and B PLAYERa device’s Filter Position 4 should be used The user should check that the IDR register is equal to

revision A or B (10h or 11h) before changing the filter setting as later revisions will default to the correct setting which may be a

different filter position number

Pseudo Code Programming Example

Care must be taken when changing the settings of the on-chip programmable loop filter The filter should only be set to the

recommended value and the additional bits in the Gain Register must not be altered Alteration of the reserved bits in the Gain

The following pseudo code outlines the proper procedure for setting the Gain Register loop filter settings to the correct value

define REV B 0x11

define REV A 0x10

define LOOP MASK 0x1F

define NEW LOOP 0x40

if (IDR k

4 REV B)

temp

4 GAIN REG

temp

4 temp

LOOP MASK

temp

4 temp l NEW LOOP

GAIN REG

4 temp

else

Do Nothing

ACCESS RULES

ADDRESS

READ

WRITE

3Dh

Always

FILT2

FILT1

FILT0

RES

Bit

Symbol

Description

D0 – D4

RES

RESERVED

Do not alter these bits The device may cease to operate properly if these bits are

changed

D5–D7

FILT0

FILT2

FILT1

FILTER SELECTION k0 1 2l

The Filter Selection k0 1 2l bits select one of five on-chip CGM

loop filters

Note

Filter combinations that are not specified or recommended should not be used and may result in non-optimal device

performance

FILT2

FILT1

FILT0

FP0 Filter Position 0

FP1 Filter Position 1

FP2 Filter Position 2 This is the filter selected after reset on the

revision A and B PLAYERa devices

FP3 Filter Position 3

FP4 Filter Position 4 This is the recommended filter position for

the revision A and B PLAYERa devices

DP83256 Datasheet(PDF) 87 Page - National Semiconductor (TI)

DP83256 Datasheet(HTML) 87 Page - National Semiconductor (TI)

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