DP83256 datasheet(53/144 Pages) NSC

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50 Registers (Continued)

59 CURRENT RECEIVE STATE REGISTER (CRSR)

The Current Receive State Register represents the current line state being detected by the Receiver Block When the Receiver

Block recognizes a new Line State the bits corresponding to the previous line state are cleared and the bits corresponding to

the new line state are set

During the reset process (ERSTeGND) the Receiver Block is forced to Line State Unknown (ie the Line State Unknown bit

(LSU) is set to 1)

Note

Users are discouraged from writing to this register An attempt to write into this register will cause the PLAYERa device to ignore the Control Bus write cycle

and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1

ACCESS RULES

ADDRESS

READ

WRITE

08h

Always

Write Reject

RES

LSU

LS2

LS1

LS0

Bit

Symbol

Description

LS0 LS1

LINE STATEk0 1 2l

These bits represent the current Line State being detected by the Receiver Block

Once the Receiver Block recognizes a new line state the bits corresponding to the previous line state are

D1 D2

LS2

cleared and the bits corresponding to the new line state are set

LS2

LS1

LS0

000

Active Line State (ALS)

Received a JK symbol pair (11000 10001) possibly followed

by data symbols

001

Idle Line State (ILS)

Received a minimum of two consecutive Idle symbol pairs

(11111 11111)

010

No Signal Detect (NSD)

The Signal Detect (SD) has been deasserted indicating that

the PLAYERa device is not receiving data from the PMD receiver or that clock detect is

not being received from the Clock Recovery Module SD is ignored during internal

loopback

Note

NSD is the default value when the device is in Stop mode However while in Stop mode certain data

patterns entering the Receiver Block may cause the PLAYERa to set LS0 Therefore the user may see

either the NSD (010) or Reserved Value (011) during Stop mode

011

Reserved

Reserved for future use

100

Master Line State (MLS)

Received a minimum of 8 consecutive Halt-Quiet symbol

pairs (00100 00000)

101

Halt Line State (HLS)

Received a minimum of 8 consecutive Halt symbol pairs

(00100 00100)

110

Quiet Line State (QLS)

Received a minimum of 8 consecutive Quiet symbol pairs

(00000 00000)

111

Noise Line State (NLS)

Detected a minimum of 16 noise events Refer to the Receiver

Block description for further information on noise events

LSU

LINE STATE UNKNOWN

The Receiver Block has not detected the minimum conditions to enter a known

line state When the Line State Unknown bit is set LSk20l represent the most recently known line state

D4-D7

RES

RESERVED

Reserved for future use

Note

Users are discouraged from using these bits The reserved bits are reset to 0 during the reset process They may be set or cleared

without any effects to the functionality of the PLAYERa device

DP83256 Datasheet(PDF) 53 Page - National Semiconductor (TI)

DP83256 Datasheet(HTML) 53 Page - National Semiconductor (TI)

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