DP83256 datasheet(46/144 Pages) NSC

46 / 144 page

50 Registers (Continued)

Bit

Symbol

Description

CWI

CONDITIONAL WRITE INHIBIT

Set to 1 when bits within mentioned registers do not match bits in the

corresponding compare register This bit ensures that new (ie unread) data is not inadvertently cleared while old

data is being cleared through the Control Bus Interface

This bit is set to 1 to indicate that a bit in a condition write register was not written because it had changed since

the previous read The following registers are affected

Interrupt Condition Register (Register 02 ICR)

Current Transmit State Register (Register 04 CTSR)

Receive Condition Register A (Register 09 RCRA)

Receive Condition Register B (Register 0A RCRB)

CMT Condition Register (Register 20 CMTCR)

The previous registers are affected when they differ from the value of the corresponding bit in the following

registers respectively

Interrupt Condition Compare Register (Register 1A ICCR)

Current Transmit State Compare Register (Register 1B CTSCR)

Receive Condition Compare Register A (Register 1C RCCRA)

Receive Condition Compare Register B (Register 1D RCCRB)

CMT Condition Compare Register (Register 1F CMTCCR)

This bit must be cleared by software Note that this differs from the MACSI BMAC and BSI device bits of the same

name

The Configuration Register (Register 01 CR) can not be written to during scrubbing

LEMT

LINK ERROR MONITOR THRESHOLD

This bit is set to 1 when the internal 8-bit Link Error Monitor Counter

reaches zero It will remain set and is cleared by software

During the reset process (ie ERSTeGND) the Link Error Monitor Threshold bit is set to 1 because the Link

Error Monitor Counter is initialized to zero

RCA

RECEIVE CONDITION A

This bit is set to 1 when

1 One or more bits in the Receive Condition Register A (RCRA) is set to 1 and

2 The corresponding mask bits in the Receive Condition Mask Register A (RCMRA) are also set to 1

In order to clear (ie set to 0) the Receive Condition A bit the bits within the Receive Condition Register A that are

set to 1 must first be either cleared or masked

RCB

RECEIVE CONDITION B

This bit is set to 1 when

1 One or more bits in the Receive Condition Register B (RCRB) is set to 1 and

2 The corresponding mask bits in the Receive Condition Mask Register A (RCMRB) are also set to 1

In order to clear (ie set to 0) the Receive Condition B bit the bits within the Receive Condition Register B that are

set to 1 must first be either cleared or masked

UDI

USER DEFINABLE INTERRUPT

This bit is set to 1 when one or any combination of the Sense Bits (SB0 SB1 or

SB2) in the User Definable Register (UDR) are set to 1

In order to clear (ie set to 0) the User Definable Interrupt Bit all Sense Bits must be set to 0

DP83256 Datasheet(PDF) 46 Page - National Semiconductor (TI)

DP83256 Datasheet(HTML) 46 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL