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AT94K Datasheet(PDF) 8 Page - ATMEL Corporation |
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AT94K Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 192 page  8 AT94K Series FPSLIC Rev. 1138F–FPSLI–06/02 Cell Connections Figure 5(a) depicts direct connections between an FPGA cell and its eight nearest neighbors. Figure 5(b) shows the connections between a cell five horizontal local buses (one per busing plane) and five vertical local buses (one per busing plane). Figure 5. Cell Connections The Cell Figure 6 depicts the AT40K FPGA embedded core logic cell. Configuration bits for separate muxes and pass gates are independent. All permutations of programmable muxes and pass gates are legal. Vn is connected to the vertical local bus in plane n. Hn is connected to the hor- izontal local bus in plane n. A local/local turn in plane n is achieved by turning on the two pass gates connected to Vn and Hn. Up to five simultaneous local/local turns are possible. The logic cell can be configured in several “modes”. The logic cell flexibility makes the FPGA architecture well suited to all digital design application areas, see Figure 7. The IDS layout tool automatically optimizes designs to utilize the cell flexibility. (a) Cell-to-Cell Connections (b) Cell-to-Bus Connections W X Y Z L WXYZL Y X Y Y Y X XX CELL CELL CELL CELL CELL CELL CELL CELL CELL CELL |
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