AT94K datasheet(76/192 Pages) ATMEL

76 / 192 page

AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02

EXTEST; $0

Mandatory JTAG instruction for selecting the Boundary-Scan Chain as Data Register for test-

ing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control,

Output Data, and Input Data are all accessible in the scan chain. For Analog circuits having

off-chip connections, the interface between the analog and the digital logic is in the scan

chain. The contents of the latched outputs of the Boundary-Scan chain are driven out as soon

as the JTAG IR-register is loaded by the EXTEST instruction.

The active states are:

•

Capture-DR: Data on the external pins are sampled into the Boundary-Scan Chain.

•

Shift-DR: The Internal Scan Chain is shifted by the TCK input.

•

Update-DR: Data from the scan chain is applied to output pins.

IDCODE; $1

Optional JTAG instruction selecting the 32-bit ID register as Data Register. The ID register

consists of a version number, a device number and the manufacturer code chosen by JEDEC.

This is the default instruction after power-up.

The active states are:

•

Capture-DR: Data in the IDCODE register is sampled into the Boundary-Scan Chain.

•

Shift-DR: The IDCODE scan chain is shifted by the TCK input.

SAMPLE_PRELOAD; $2

Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the

input/output pins without affecting the system operation. However, the output latches are not

connected to the pins. The Boundary-Scan Chain is selected as Data Register.

The active states are:

•

Capture-DR: Data on the external pins are sampled into the Boundary-Scan Chain.

•

Shift-DR: The Boundary-Scan Chain is shifted by the TCK input.

•

Update-DR: Data from the Boundary-Scan chain is applied to the output latches. However,

the output latches are not connected to the pins.

AVR_RESET; $C

The AVR specific public JTAG instruction for forcing the AVR device into the Reset Mode or

releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one

bit Reset Register is selected as Data Register. Note that the reset will be active as long as

there is a logic “1” in the Reset Chain. The output from this chain is not latched.

The active state is:

•

Shift-DR: The Reset Register is shifted by the TCK input.

BYPASS; $F

Mandatory JTAG instruction selecting the Bypass Register for Data Register.

The active states are:

•

Capture-DR: Loads a logic “0” into the Bypass Register.

•

Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

Boundary-scan Chain

The Boundary-Scan chain has the capability of driving and observing the logic levels on the

AVR’s digital I/O pins.

Scanning the Digital

Port Pins

Figure 43 shows the boundary-scan cell for bi-directional port pins with pull-up function. The

cell consists of a standard boundary-scan cell for the pull-up function, and a bi-directional pin

cell that combines the three signals Output Control (OC), Output Data (OD), and Input Data

(ID), into only a two-stage shift register.

AT94K Datasheet(PDF) 76 Page - ATMEL Corporation

AT94K Datasheet(HTML) 76 Page - ATMEL Corporation

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