AT94K datasheet(68/192 Pages) ATMEL

68 / 192 page

AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02

JTAG Interface and

On-chip Debug

System

Features

• JTAG (IEEE std. 1149.1 Compliant) Interface

• AVR I/O Boundary-scan Capabilities According to the JTAG Standard

• Debugger Access to:

– All Internal Peripheral Units

– AVR Program and Data SRAM

– The Internal Register File

– Program Counter/Instruction

– FPGA/AVR Interface

• Extensive On-chip Debug Support for Break Conditions, Including

– Break on Change of Program Memory Flow

– Single Step Break

– Program Memory Breakpoints on Single Address or Address Range

– Data Memory Breakpoints on Single Address or Address Range

– FPGA Hardware Break

– Frame Memory Breakpoint on Single Address

• On-chip Debugging Supported by AVR Studio version 4 or above

Overview

The AVR IEEE std. 1149.1 compliant JTAG interface is used for on-chip debugging.

The On-Chip Debug support is considered being private JTAG instructions, and distributed

within ATMEL and to selected third-party vendors only.

Figure 39 shows a block diagram of the JTAG interface and the On-Chip Debug system. The

TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller

selects either the JTAG Instruction Register or one of several Data Registers as the scan

chain (shift register) between the TDI - input and TDO - output. The Instruction Register holds

JTAG instructions controlling the behavior of a Data Register.

Of the Data Registers, the ID-Register, Bypass Register, and the AVR I/O Boundary-Scan

Chain are used for board-level testing. The Internal Scan Chain and Break-Point Scan Chain

are used for On-Chip debugging only.

The Test Access

Port – TAP

The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these

pins constitute the Test Access Port - TAP. These pins are:

•

TMS: Test Mode Select. This pin is used for navigating through the TAP-controller state

machine.

•

TCK: Test Clock. JTAG operation is synchronous to TCK

•

TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data

•

TDO: Test Data Out. Serial output data from Instruction register or Data Register

The IEEE std. 1149.1 also specifies an optional TAP signal; TRST - Test ReSeT - which is not

provided.

When the JTAGEN bit is unprogrammed, these four TAP pins revert to normal operation.

When programmed, the input TAP signals are internally pulled High and the JTAG is enabled

for Boundary-Scan. System Designer sets this bit by default.

For the On-Chip Debug system, in addition the RESET pin is monitored by the debugger to be

able to detect external reset sources. The debugger can also pull the RESET pin Low to reset

the whole system, assuming only open collectors on reset line are used in the application.

AT94K Datasheet(PDF) 68 Page - ATMEL Corporation

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