AT94K datasheet(44/192 Pages) ATMEL

44 / 192 page

AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02

X-register,

Y-register and

Z-register

Registers R26..R31 have some added functions to their general-purpose usage. These regis-

ters are address pointers for indirect addressing of the SRAM. The three indirect address

registers X, Y and Z have functions as fixed displacement, automatic increment and decre-

ment (see the descriptions for the different instructions).

ALU – Arithmetic

Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general-purpose

working registers. Within a single clock cycle, ALU operations between registers in the register

file are executed. The ALU operations are divided into three main categories – arithmetic, log-

ical and bit-functions.

Multiplier Unit

The high-performance AVR Multiplier operates in direct connection with all the 32 general-pur-

pose working registers. This unit performs 8 x 8 multipliers every two clock cycles. See

multiplier details on page 106.

SRAM Data

Memory

External data SRAM (or program) cannot be used with the FPSLIC AT94K family.

The five different addressing modes for the data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the register

file, registers R26 to R31 feature the indirect addressing pointer registers.

The Indirect with Displacement mode features a 63 address locations reach from the base

address given by the Y- or Z-register.

When using register indirect addressing modes with automatic Pre-decrement and Post-incre-

ment, the address registers X, Y and Z are decremented and incremented.

The entire data address space including the 32 general-purpose working registers and the 64

I/O registers are all accessible through all these addressing modes. See the next section for a

detailed description of the different addressing modes.

Program and Data

Addressing Modes

The embedded AVR core supports powerful and efficient addressing modes for access to the

program memory (SRAM) and data memory (SRAM, Register File and I/O Memory). This sec-

tion describes the different addressing modes supported by the AVR architecture.

The operand is contained in register d (Rd).

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

I/O Direct

Operand address is contained in 6 bits of the instruction word.

n is the destination or source

Data Direct

A 16-bit data address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the

destination or source register.

Data Indirect with Displacement

Operand address is the result of the Y- or Z-register contents added to the address contained

in 6 bits of the instruction word.

AT94K Datasheet(PDF) 44 Page - ATMEL Corporation

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