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AT94K Datasheet(PDF) 40 Page - ATMEL Corporation

Part # AT94K
Description  5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE
PDF  192 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT94K Datasheet(HTML) 40 Page - ATMEL Corporation

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40
AT94K Series FPSLIC
Rev. 1138F–FPSLI–06/02
Pin Descriptions
V
CC
Supply voltage
GND
Ground
PortD (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal programmable pull-up resistors. The Port
D output buffers can be programmed to sink/source either 6 or 20 mA (SCR54 – see “System
Control Register – FPGA/AVR” on page 30). As inputs, Port D pins that are externally pulled
Low will source current if the programmable pull-up resistors are activated.
The Port D pins are input with pull-up when a reset condition becomes active, even if the clock
is not running. On lower pin count packages Port D may not be available. Check the Pin List
for details.
PortE (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal programmable pull-up resistors. The Port
E output buffers can be programmed to sink/source either 6 or 20 mA (SCR55 – see “System
Control Register – FPGA/AVR” on page 30). As inputs, Port E pins that are externally pulled
Low will source current if the pull-up resistors are activated.
Port E also serves the functions of various special features. See Table 46 on page 149.
The Port E pins are input with pull-up when a reset condition becomes active, even if the clock
is not running
RX0
Input (receive) to UART(0) – See SCR52
TX0
Output (transmit) from UART(0) – See SCR52
RX1
Input (receive) to UART(1) – See SCR53
TX1
Output (transmit) from UART(1) – See SCR53
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
CLS
Clear Signed Test Flag
S
← 0S
1
SEV
Set Two’s Complement Overflow
V
← 1V
1
CLV
Clear Two’s Complement Overflow
V
← 0V
1
SET
Set T in SREG
T
← 1T
1
CLT
Clear T in SREG
T
← 0T
1
SEH
Set Half-carry Flag in SREG
H
← 1H
1
CLH
Clear Half-carry Flag in SREG
H
← 0H
1
NOP
No Operation
None
1
SLEEP
Sleep
(See specific description for Sleep)
None
1
WDR
Watchdog Reset
(See specific description for WDR)
None
1
BREAK
Break
For on-chip debug only
None
N/A
Instruction Set Summary (Continued)
Mnemonics
Operands
Description
Operation
Flags
#Clock



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