AT94K datasheet(22/192 Pages) ATMEL

22 / 192 page

AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02

Program and

Data SRAM

Up to 36 Kbytes of 15 ns dual-port SRAM reside between the FPGA and the AVR. This SRAM

is used by the AVR for program instruction and general-purpose data storage. The AVR is

connected to one side of this SRAM; the FPGA is connected to the other side. The port con-

nected to the FPGA is used to store data without using up bandwidth on the AVR system data

bus.

The FPGA core communicates directly with the data SRAM(1) block, viewing all SRAM mem-

ory space as 8-bit memory.

Note:

1. The unused bits for the FPGA-SRAM address must tie to ‘0’ because there is no pull-down

circuitry.

For the AT94K10 and AT94K40, the internal program and data SRAM is divided into three

blocks: 10 Kbytes x 16 dedicated program SRAM, 4 Kbytes x 8 dedicated data SRAM and 6

Kbytes x 16 or 12 Kbytes x 8 configurable SRAM, which may be swapped between program

and data memory spaces in 2 Kbytes x 16 or 4 Kbytes x 8 partitions.

For the AT94K05, the internal program and data SRAM is divided into three blocks: 4 Kbytes

16 dedicated program SRAM, 4 Kbytes x 8 dedicated data SRAM and 6 Kbytes x 16 or 12

Kbytes x 8 configurable SRAM, which may be swapped between program and data memory

spaces in 2 Kbytes x 16 or 4 Kbytes x 8 partitions.

The addressing scheme for the configurable SRAM partitions prevents program instructions

from overwriting data words and vice versa. Once configured (SCR41:40 – See “System Con-

trol Register – FPGA/AVR” on page 30.), the program memory space remains isolated from

the data memory space. SCR41:40 controls internal muxes. Write enable signals allow the

memory to be safely segmented. Figure 19 shows the FPSLIC configurable allocation SRAM

memory.

AT94K Datasheet(PDF) 22 Page - ATMEL Corporation