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AT94K Datasheet(PDF) 6 Page - ATMEL Corporation |
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AT94K Datasheet(HTML) 6 Page - ATMEL Corporation |
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6 / 192 page ![]() 6 AT94K Series FPSLIC Rev. 1138F–FPSLI–06/02 The Busing Network Figure 3. Busing Network Figure 4 depicts one of five identical FPGA busing planes. Each plane has three bus resources: a local-bus resource (the middle bus) and two express-bus resources. Bus resources are connected via repeaters. Each repeater has connections to two adjacent local- bus segments and two express-bus segments. Each local-bus segment spans four cells and connects to consecutive repeaters. Each express-bus segment spans eight cells and bypasses a repeater. Repeaters regenerate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. Although not shown, a local bus can bypass a repeater via a programmable pass gate, allowing long on-chip tri-state buses to be created. Lo ca l /l oc al tu r ns ar e im pl e m e nte d th ro ug h p as s g a tes i n the c el l -b us i nt er fac e. Express/express turns are implemented through separate pass gates distributed throughout the array. = I/O Pad = AT40K Cell = Repeater Row = Repeater = RAM Block Interface to AVR |
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