AT94K datasheet(26/192 Pages) ATMEL

26 / 192 page

AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02

BSide

The B side is not partitioned; the FPGA (and AVR debug mode) views the memory space as

36 x 8 Kbytes.

•

The B side is accessed by the FPGA/Configuration Logic.

•

The B side is accessed by the AVR with ST and LD instructions in DBG mode for code

self-modify.

To activate the debug mode and allow the AVR to access the program code space (with

ST – seeFigure21 – and LD – see Figure 22 – instructions), the DBG bit (bit 1) of the

SFTCR $3A ($5A) register has to be set. When this bit is set, SCR36 and SCR37 are

ignored – you can overwrite anything in the AVR program memory.

The FPGA memory access interface should be disabled while in debug mode. This is to

ensure that there is no contention between the FPGA address and data signals and the

AVR-generated address and data signals. To ensure the AVR has control over the “B

side” memory interface, the FMXOR bit (bit 3) of the SFTCR $3A ($5A) register should be

used in conjunction with the SCR63 system control register bit.

The FMXOR bit is XORed with the System Control Register’s Enable FPGA SRAM Inter-

face bit (SCR63). The behavior when this bit is set to 1 is dependent on how the SCR was

initialized. If the Enable FPGA SRAM Interface bit (SCR63) in the SCR is 0, the FMXOR

bit enables the FPGA SRAM Interface when set to 1. If the Enable FPGA SRAM Interface

bit in the SCR is 1, the FMXOR bit disables the FPGA SRAM Interface when set to 1. Dur-

ing AVR reset, the FMXOR bit is cleared by the hardware.

Even though the FPGA (and AVR debug mode) views the memory space as

36 x 8 Kbytes, an awareness of the 2K x 8 partitions (or SRAM labels) is required if Frame

(and AVR debug mode) read/writes are to be meaningful to the AVR.

•

AVR data to FPGA addressing is 1:1 mapping.

•

AVR program to FPGA addressing requires 16-bit to 8-bit mapping and an understanding

of the partitions in Table 6.

Table 5. AVR Data Decode for SRAM 0:17 (16K8)

Address Range

SRAM

Comments

$07FF – $0000

$0FFF – $0800

AVR Data Read/Write

$17FF – $1000

$1FFF – $1800

CR41:40 = 11,10,01

$27FF – $2000

$2FFF – $2800

CR41:40 = 11,10

$37FF – $3000

$3FFF – $3800

CR41:40 = 11

Table 6. Summary Table for AVR and FPGA SRAM Addressing

SRAM

FPGA and AVR DBG

Address Range

AVR Data

Address Range

AVR PC Address Range

$0000 - $07FF

$0800 - $0FFF

(1)

$1000 - $17FF

$3800 - $3FFF (LS Byte)

(1)

$1800 - $1FFF

$3800 - $3FFF (MS Byte)

(1)

$2000 - $27FF

$3000 - $37FF (LS Byte)

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