AT94K datasheet(74/192 Pages) ATMEL

74 / 192 page

AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02

undetermined state when exiting the test mode. If needed, the BYPASS instruction can be

issued to make the shortest possible scan chain through the device. The AVR can be set in

the reset state either by pulling the external AVR RESET pin Low, or issuing the AVR_RESET

instruction with appropriate setting of the Reset Data Register.

The EXTEST instruction is used for sampling external pins and loading output pins with data.

The data from the output latch will be driven out on the pins as soon as the EXTEST instruc-

tion is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be

used for setting initial values to the scan ring, to avoid damaging the board when issuing the

EXTEST instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snap-

shot of the AVR’s external pins during normal operation of the part.

The JTAG Enable bit must be programmed and the JTD bit in the I/O register MCUR must be

cleared to enable the JTAG Test Access Port.

When using the JTAG interface for Boundary-Scan, using a JTAG TCK clock frequency higher

than the internal chip frequency is possible. The chip clock is not required to run.

Data Registers

The Data Registers are selected by the JTAG instruction registers described in section

“Boundary-scan Specific JTAG Instructions” on page 75. The data registers relevant for

Boundary-Scan operations are:

•

Bypass Register

•

Device Identification Register

•

AVR Reset Register

•

AVR Boundary-Scan Chain

Bypass Register

The Bypass register consists of a single shift-register stage. When the Bypass register is

selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-

DR controller state. The Bypass register can be used to shorten the scan chain on a system

when the other devices are to be tested.

Device

Identification

Figure 41 shows the structure of the Device Identification register.

Figure 41. The format of the Device Identification Register

Version

Version is a 4-bit number identifying the revision of the component. The relevant version num-

bers are shown in Table 17.

MSB

LSB

Bit

312827

Device ID

Version

Part Number

Manufacturer ID

4bits

16bits

11 bits

1 bit

Table 17. JTAG Part Version

Device

Version (Binary Digits)

AT94K05

–

AT94K10

0010

AT94K40

–

AT94K Datasheet(PDF) 74 Page - ATMEL Corporation

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