AT94K datasheet(42/192 Pages) ATMEL

42 / 192 page

AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02

No Clock/Oscillator

Source

When not in use, for low static IDD, add a pull-down resistor to XTAL1.

Figure 26. No Clock/Oscillator Connections

Timer Oscillator

For the timer oscillator pins, TOSC1 and TOSC2, the crystal is connected directly between the

pins. The oscillator is optimized for use with a 32.768 kHz watch crystal. An external clock sig-

nal applied to this pin goes through the same amplifier having a bandwidth of 1 MHz. The

external clock signal should therefore be in the range

0Hz – 1MHz.

Figure 27. Time Oscillator Connections

Architectural

Overview

The AVR uses a Harvard architecture concept – with separate memories and buses for pro-

gram and data. The program memory is accessed with a single level pipeline. While one

instruction is being executed, the next instruction is pre-fetched from the program memory.

This concept enables instructions to be executed in every clock-cycle. The program memory is

in-system programmable SRAM memory. With a few exceptions, AVR instructions have a sin-

gle 16-bit word format, meaning that every program memory address contains a single 16-bit

instruction.

During interrupts and subroutine calls, the return address program counter (PC) is stored on

the stack. The stack is effectively allocated in the general data SRAM, as a consequence, the

stack size is only limited by the total SRAM size and the usage of the SRAM. All user pro-

grams must initialize the Stack Pointer (SP) in the reset routine (before subroutines or

interrupts are executed). The 16-bit stack pointer is read/write accessible in the I/O space.

The data SRAM can be easily accessed through the five different addressing modes sup-

ported in the AVR architecture.

A flexible interrupt module has its control registers in the I/O space with an additional global

interrupt enable bit in the status register. All the different interrupts have a separate interrupt

vector in the interrupt vector table at the beginning of the program memory. The different inter-

rupts have priority in accordance with their interrupt vector position. The lower the interrupt

vector address, the higher the priority.

The memory spaces in the AVR architecture are all linear and regular memory maps.

XTAL2

XTAL1

GND

RPD

RPD = 4.7 KΩ

TOSC2

TOSC1

C1 = 33 pF

C2 = 27 pF

RB = 10M

RS = 200K

AT94K Datasheet(PDF) 42 Page - ATMEL Corporation

AT94K Datasheet(HTML) 42 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL