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TMS320VC5502 Datasheet(PDF) 102 Page - Texas Instruments |
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TMS320VC5502 Datasheet(HTML) 102 Page - Texas Instruments |
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102 / 189 page  www.ti.com 3.14.3 IPORT Interface TMS320VC5502 Fixed-Point Digital Signal Processor SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004 Table 3-52. DPORT Bus Error Register Bit Field Description BIT NAME BIT NO. ACCESS RESET VALUE DESCRIPTION Reserved 15-13 R 000 Reserved EMIFTO 12 R 0 EMIFTO bit • EMIFTO = 0: No error • EMIFTO = 1: Error 1 error Reserved 11-0 R 000000000000 Reserved The IPORT interfaces the I-Cache to the EMIF module. The ICACHETO bit of the IPORT Bus Error Register (IERR) can be used to determine if a time-out error has occurred during an ICACHE access to external memory. The time-out feature is enabled through the EMIFTOEN bit of the Time-Out Control Register (TOCR). The IPORT can be placed into idle through the IPORTI bit of the Idle Control Register (ICR) and executing the IDLE instruction. The IPORT will go into idle when there are no new requests from the ICACHE. When the IPORT is in idle, it will stop accepting new requests from the CPU, it is important that the program flow not use external memory in this case. If there are requests from the CPU, the IPORT will not respond and hang. The ICR register will generate a bus error if the IPORT is idled without the CPU domain being in idle. 3.14.3.1 IPORT Bus Error Register (IERR) The IPORT Bus Error Register bit layout is shown in Figure 3-48 and the bits are described in Table 3-53. 15 13 12 11 8 Reserved ICACHETO Reserved R, 000 R, 0 R, 0000 7 0 Reserved R, 00000000 LEGEND: R = Read, W = Write, n = value at reset Figure 3-48. IPORT Bus Error Register Layout (0x0302) Table 3-53. IPORT Bus Error Register Bit Field Description BIT NAME BIT NO. ACCESS RESET VALUE DESCRIPTION Reserved 15-13 R 000 Reserved ICACHETO 12 R 0 ICACHETO bit • ICACHETO = 0: No error • ICACHETO = 1: A time-out error occurred during an ICACHE access to external memory. Reserved 11-0 R 000000000000 Reserved 102 Functional Overview |
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