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3.14.5

Time-Out Control Register (TOCR)

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

The Time-Out Control Register can be used to select whether or not a time-out error is generated when

an access to a disabled/idled peripheral module occurs. If the CPU or DMA access a disabled/idle

peripheral module and 512 CPU clock cycles pass without an acknowledgement from the peripheral

module, then a time-out error will be sent to the corresponding module if bit 1 in the Time-Out Control

using the bus error interrupt (BERR) (see Section 3.17, Interrupts, for more information on interrupts). If

the DMA gets a time-out error, it will set the TIMEOUT bit in the DMA Status Register (DMACSR) and

generate

time-out

error

that

can

serviced

through

software

the

CPU

[see

the

TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (literature number

SPRU613) for more information on using this feature of the DMA].

The Time-Out Control Register can also be used to select whether or not a time-out error is generated

when a memory access through the EMIF module stalls for more than 512 CPU clock cycles. It is

recommended that this feature not be used for it can cause unexpected results.

Reserved

R, 00000000

Reserved

EMIFTOEN

PERITOEN

R, 000000

R/W, 0

R/W, 1

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-50. Time-Out Control Register Layout (0x9000)

Table 3-55. Time-Out Control Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15-2

00000000000000 Reserved

EMIFTOEN

R/W

EMIF time-out control bit

•

EMIFTOEN = 0: A time-out error is not generated when an EMIF

access stalls for more than 512 CPU clock cycles.

•

EMIFTOEN = 1: A time-out error is generated when an EMIF

access stalls for more than 512 CPU clock cycles.

PERITOEN

R/W

Peripheral module time-out control bit

•

PERITOEN = 0: A time-out error is not generated when a CPU

access to a disabled/idle peripheral module stalls for more than

512 CPU clock cycles.

•

PERITOEN = 1: A time-out error is generated when a CPU

access to a disabled/idle peripheral module stalls for more than

512 CPU clock cycles.

104

Functional Overview

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