TMS320VC5502 datasheet(128/189 Pages) TI

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5.4

Electrical Characteristics Over Recommended Operating Case Temperature Range

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

(Unless Otherwise Noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DVDD = 3.3 ± 0.3 V,

VOH

High-level output voltage

2.4

IOH = MAX

VOL

Low-level output voltage

IOL = MAX

0.4

Bus holders enabled

Output-only or input/output pins

DVDD = MAX,

–300

300

Input current for

with bus holders

VO = VSS to DVDD

IIZ

outputs in high im-

µA

pedance

All other output-only or

DVDD = MAX,

–5

input/output pins

VI = VSS to DVDD

DVDD = MAX,

Input pins with internal pulldown

–5

300

VI = VSS to DVDD

DVDD = MAX,

X2/CLKIN

–50

VI = VSS to DVDD

Input current

µA

Pullup enabled

Input pins with internal pullup

DVDD = MAX,

–300

VI = VSS to DVDD

DVDD = MAX,

All other input-only pins

–5

VI = VSS to DVDD

CVDD = Nominal

IDDC

CVDD supply current(1)

CPU clock = 300 MHz

239

TC = 25°C

DVDD = Nominal

IDDD

DVDD supply current(1)

CPU clock = 300 MHz

TC = 25°C

PVDD = Nominal

IDDP

PVDD supply current(1)

20-MHz clock input,

APLL mode = x15

Input capacitance

Output capacitance

(1)

Current draw is highly application-dependent. The power numbers quoted here are for the sample application described in the

TMS320VC5501/02 Power Consumption Summary application report (literature number SPRA993). The spreadsheet provided with the

application report can be used to estimate the power consumption for a particular application. The spreadsheet also contains the current

consumption that can be expected when running the DSP in its idle configurations.

The sample application can be summarized as follows:

•

Case temperature: 25

°C

•

APLL: 300 MHz

•

CPU: 85% utilization

–

Instruction cache enabled

–

CLKOUT off

•

EMIF: 75 MHz, 118% utilization, 100% writes, 32 bits, 100% switching

–

ECLKOUT1 and ECLKOUT2: Off

•

HPI: 5Mwords/second, 100% utilization, 100% writes, 100% switching

•

DMA:

–

Channel 0: 35% utilization, 32-bit elements, 100% switching (for internal memory to external memory transfers)

–

Channel 1: 1.56% utilization, 32-bit elements, 100% switching (for internal memory to McBSP0 transfers)

–

Channel 2: 1.56% utilization, 32-bit elements, 100% switching (for McBSP1 to internal memory transfers)

–

Channels 3 and 4: 0% utilization (reserved for UART transfers)

–

Channel 5: 60% utilization (for internal memory to internal memory transfers using Watchdog Timer event)

•

McBSP0: 25 MHz, 100% utilization, 100% switching

•

Timer0: 5 MHz, 100% utilization, 100% switching

•

Timer1: 10 MHz, 100% utilization, 100% switching

•

WD Timer: 30 MHz, 100% utilization, 100% switching

•

UART: 9600 baud, 100% utilization

•

All other peripherals use 0 MHz, 0% utilization

Specifications

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TMS320VC5502 Datasheet(PDF) 128 Page - Texas Instruments

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