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5.6.2

Layout Considerations

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

The recommended ESR is presented as a maximum, and theoretically, a crystal with a lower maximum ESR

might seem to meet these specifications. However, it is recommended that crystals with actual maximum ESR

specifications as shown in Table 5-1 be used since this will result in maximum crystal performance reliability.

Since parasitic capacitance, inductance, and resistance can be significant in this and any circuit, good PC board

layout practices should always be observed when planning trace routing to the discrete components used in this

oscillator circuit. Specifically, the crystal and the associated discrete components should be located as close to

the DSP as physically possible. Also, X1 and X2/CLKIN traces should be separated as soon as possible after

routing away from the DSP to minimize parasitic capacitance between them, and a ground trace should be run

between these two signal lines. This also helps to minimize stray capacitance between these two signals.

Specifications

131

TMS320VC5502 Datasheet(PDF) 131 Page - Texas Instruments