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TMS320VC5502 Datasheet(PDF) 134 Page - Texas Instruments

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Part # TMS320VC5502
Description  Fixed-Point Digital Signal Processor
PDF  189 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320VC5502 Datasheet(HTML) 134 Page - Texas Instruments

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(A ) The waveform relationship of CLKIN to CLKOUT depends on the multiply and divide factors chosen for the APLL synthesis and on the system
clock selected to drive CLKOUT. The waveform relationship shown in this figure is intended to illustrate the timing parameters only and may
differ based on configuration.
C1
C7
C6
C3
C4
C8
CLKIN
CLKOUT
C5
C9
Bypass Mode
5.6.5
EMIF Clock Options
TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004
Figure 5-4. External Multiply-by-N Clock Timings
Table 5-6 through Table 5-8 assume testing over recommended operating conditions (see Figure 5-5 through
Figure 5-7).
Table 5-6. EMIF Timing Requirements for ECLKIN
(1) (2)
VC5502-200
VC5502-300
NO.
UNIT
MIN
MAX
E7
tc(EKI)
Cycle time, ECLKIN
10
16P
ns
E8
tw(EKIH)
Pulse duration, ECLKIN high
0.4 * tc(EKI)
ns
E9
tw(EKIL)
Pulse duration, ECLKIN low
0.4 * tc(EKI)
ns
E10
tt(EKI)
Transition time, ECLKIN
2
ns
(1)
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
(2)
The reference points for the rise and fall transitions are measured at VIL MAX and VIHMIN.
Table 5-7. EMIF Switching Characteristics for ECLKOUT1
(1) (2) (3)
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MIN
MAX
E1
tc(EKO1)
Cycle time, ECLKOUT1
E – 1
E + 1
ns
E2
tw(EKO1H)
Pulse duration, ECLKOUT1 high
EH – 1
EH + 1
ns
E3
tw(EKO1L)
Pulse duration, ECLKOUT1 low
EL – 1
EL + 1
ns
E4
tt(EKO1)
Transition time, ECLKOUT1
1
ns
E5
td(EKIH-EKO1H)
Delay time, ECLKIN high to ECLKOUT1 high
3
13
ns
E6
td(EKIL-EKO1L)
Delay time, ECLKIN low to ECLKOUT1 low
3
13
ns
(1)
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2)
E = the EMIF input clock (CPU clock, CPU/2 clock, or CPU/4 clock) period in ns for EMIF.
(3)
EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIF.
Specifications
134



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