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5.7

Memory Timings

5.7.1

Asynchronous Memory Timings

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-9 and Table 5-10 assume testing over recommended operating conditions (see Figure 5-8 and

Figure 5-9).

Table 5-9. Asynchronous Memory Cycle Timing Requirements for ECLKIN

(1) (2)

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

tsu(EDV-AREH)

Setup time, EMIF.Dx valid before EMIF.ARE high

th(AREH-EDV)

Hold time, EMIF.Dx valid after EMIF.ARE high

tsu(ARDY-EKO1H)

Setup time, EMIF.ARDY valid before ECLKOUT1 high

3.5

th(EKO1H-ARDY)

Hold time, EMIF.ARDY valid after ECLKOUT1 high

(1)

To ensure data setup time, simply program the strobe width wide enough. EMIF.ARDY is internally synchronized. The EMIF.ARDY

signal is recognized in the cycle for which the setup and hold time is met. To use EMIF.ARDY as an asynchronous input, the pulse width

of the EMIF.ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.

(2)

RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters

are programmed via the EMIF CE space control registers.

Table 5-10. Asynchronous Memory Cycle Switching Characteristics for ECLKOUT1

(1) (2) (3)

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

tosu(SELV-AREL)

Output setup time, select signals valid to EMIF.ARE low

RS * E – 1.5

toh(AREH-SELIV)

Output hold time, EMIF.ARE high to select signals invalid

RH * E – 1.5

td(EKO1H-AREV)

Delay time, ECLKOUT1 high to EMIF.ARE valid

1.5

tosu(SELV-AWEL)

Output setup time, select signals valid to EMIF.AWE low

WS * E – 1.5

toh(AWEH-SELIV)

Output hold time, EMIF.AWE high to select signals invalid

WH * E – 1.5

A10

td(EKO1H-AWEV)

Delay time, ECLKOUT1 high to EMIF.AWE valid

1.5

(1)

RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters

are programmed via the EMIF CE space control registers.

(2)

E = ECLKOUT1 period in ns for EMIF.

(3)

Select signals for EMIF include: EMIF.CEx, EMIF.BE[3:0], EMIF.A[21:2], and EMIF.AOE; and for EMIF writes, include EMIF.D[31:0].

Specifications

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TMS320VC5502 Datasheet(PDF) 136 Page - Texas Instruments

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