TMS320VC5502 datasheet(139/189 Pages) TI

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5.7.2

Programmable Synchronous Interface Timings

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-11 and Table 5-12 assume testing over recommended operating conditions (see Figure 5-10 through

Figure 5-12).

Table 5-11. Programmable Synchronous Interface Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

PS6

tsu(EDV-EKOxH)

Setup time, read EMIF.Dx valid before ECLKOUTx high

PS7

th(EKOxH-EDV)

Hold time, read EMIF.Dx valid after ECLKOUTx high

1.5

Table 5-12. Programmable Synchronous Interface Switching Characteristics

(1)

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

PS1

td(EKOxH-CEV)

Delay time, ECLKOUTx high to EMIF.CEx valid

0.8

PS2

td(EKOxH-BEV)

Delay time, ECLKOUTx high to EMIF.BEx valid

PS3

td(EKOxH-BEIV)

Delay time, ECLKOUTx high to EMIF.BEx invalid

0.8

PS4

td(EKOxH-EAV)

Delay time, ECLKOUTx high to EMIF.Ax valid

PS5

td(EKOxH-EAIV)

Delay time, ECLKOUTx high to EMIF.Ax invalid

0.8

PS8

td(EKOxH-ADSV)

Delay time, ECLKOUTx high to EMIF.SADS/SRE valid

0.8

PS9

td(EKOxH-OEV)

Delay time, ECLKOUTx high to, EMIF.SOE valid

0.8

PS10

td(EKOxH-EDV)

Delay time, ECLKOUTx high to EMIF.Dx valid

PS11

td(EKOxH-EDIV)

Delay time, ECLKOUTx high to EMIF.Dx invalid

0.8

PS12

td(EKOxH-WEV)

Delay time, ECLKOUTx high to EMIF.SWE valid

0.8

(1)

The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2):

•

Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

•

Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

•

EMIF.CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, EMIF.CEx goes inactive after the final

command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, EMIF.CEx is active when EMIF.SOE is active

(CEEXT = 1).

•

Function of EMIF.SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, EMIF.SADS/SRE acts as EMIF.SADS with

deselect cycles (RENEN = 0). For FIFO interface, EMIF.SADS/SRE acts as EMIF.SRE with NO deselect cycles (RENEN = 1).

•

Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2

139

Specifications

TMS320VC5502 Datasheet(PDF) 139 Page - Texas Instruments

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