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5.7.3

Synchronous DRAM Timings

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-13 and Table 5-14 assume testing over recommended operating conditions (see Figure 5-13 through

Figure 5-20).

Table 5-13. Synchronous DRAM Cycle Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

SD6

tsu(EDV-EKO1H)

Setup time, read EMIF.Dx valid before ECLKOUT1 high

SD7

th(EKO1H-EDV)

Hold time, read EMIF.Dx valid after ECLKOUT1 high

Table 5-14. Synchronous DRAM Cycle Switching Characteristics

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

SD1

td(EKO1H-CEV)

Delay time, ECLKOUT1 high to EMIF.CEx valid/invalid

0.8

SD2

td(EKO1H-BEV)

Delay time, ECLKOUT1 high to EMIF.BEx valid

SD3

td(EKO1H-BEIV)

Delay time, ECLKOUT1 high to EMIF.BEx invalid

0.8

SD4

td(EKO1H-EAV)

Delay time, ECLKOUT1 high to EMIF.Ax valid

SD5

td(EKO1H-EAIV)

Delay time, ECLKOUT1 high to EMIF.Ax invalid

0.8

SD8

td(EKO1H-CASV)

Delay time, ECLKOUT1 high to EMIF.SDCAS valid

0.8

SD9

td(EKO1H-EDV)

Delay time, ECLKOUT1 high to EMIF.Dx valid

SD10

td(EKO1H-EDIV)

Delay time, ECLKOUT1 high to EMIF.Dx invalid

0.8

SD11

td(EKO1H-WEV)

Delay time, ECLKOUT1 high to EMIF.SDWE valid

0.8

SD12

td(EKO1H-RASV)

Delay time, ECLKOUT1 high to EMIF.SDRAS valid

0.8

SD13

td(EKO1H-CKEV)

Delay time, ECLKOUT1 high to EMIF.SDCKE valid

0.8

Specifications

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TMS320VC5502 Datasheet(PDF) 142 Page - Texas Instruments

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