TMS320VC5502 datasheet(146/189 Pages) TI

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ECLKOUT1

EMIF.CEx

EMIF.BE[3:0]

EMIF.A[21:2]

EMIF.D[31:0]

EMIF.AOE/SOE/SDRAS

(see Note A)

EMIF.ARE/SADS/SDCAS/SRE

(see Note A)

EMIF.AWE/SWE/SDWE

(see Note A)

MRS value

SD11

SD8

SD12

SD5

SD1

MRS

SD11

SD8

SD12

SD4

SD1

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and

EMIF.SDRAS, respectively, during SDRAM accesses.

End Self-Refresh

Self Refresh

SD13

ECLKOUT1

EMIF.CEx

EMIF.BE[3:0]

EMIF.A[21:13, 11:2]

EMIF.A12

EMIF.D[31:0]

EMIF.AOE/SOE/SDRAS

(see Note A)

EMIF.ARE/SADS/SDCAS/SRE

(see Note A)

EMIF.AWE/SWE/SDWE

(see Note A)

EMIF.SDCKE

≥ TRAS cycles

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and

EMIF.SDRAS, respectively, during SDRAM accesses.

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Figure 5-19. SDRAM MRS Command

Figure 5-20. SDRAM Self-Refresh Timings

146

Specifications

TMS320VC5502 Datasheet(PDF) 146 Page - Texas Instruments

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