TMS320VC5502 datasheet(148/189 Pages) TI

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5.9

Reset Timings

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-17 and Table 5-18 assume testing over recommended operating conditions (see Figure 5-22).

Table 5-17. Reset Timing Requirements

(1)

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

tw(RSL)

Pulse width, RESET low

2P + 5

(1)

P = the period of the clock on the X2/CLKIN pin in ns. For example, when using 20 MHz as the input clock, use P = 50 ns.

Table 5-18. Reset Switching Characteristics

(1)

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

td(RSL-EMIFHZ)

Delay time, RESET low to EMIF group high impedance(2)

GPIO4 = 0 (CLKMOD = 0)

41115P + 21

td(RSH-EMIFV)

Delay time, RESET high to EMIF group valid(2)

GPIO4 = 1 (CLKMOD = 1)

148P + 22

td(RSL-HIGHIV)

Delay time, RESET low to high group invalid(3)

GPIO4 = 0 (CLKMOD = 0)

41044P + 17

td(RSH-HIGHV)

Delay time, RESET high to high group valid(3)

GPIO4 = 1 (CLKMOD = 1)

77P + 18

td(RSL-ZHZ)

Delay time, RESET low to Z group high impedance(4)

GPIO4 = 0 (CLKMOD = 0)

41044P + 18

td(RSH-ZV)

Delay time, RESET high to Z group invalid(4)

GPIO4 = 1 (CLKMOD = 1)

77P + 19

td(RSL-IOIM)

Delay time, RESET low to Input/Output group switch to input mode(5)

td(RSL-TGLD)

Delay time, RESET low to Toggle group switch to default toggle frequency(6)

11 + 14P

(1)

P = the period of the clock on the X2/CLKIN pin in ns. For example, when using 20 MHz as the input clock, use P = 50 ns.

(2)

EMIF group: EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, EMIF.AWE/SWE/SDWE, EMIF.ARDY, EMIF.CE0,

EMIF.CE1, EMIF.CE2, EMIF.CE3, EMIF.BE0, EMIF.BE1, EMIF.BE2, EMIF.BE3, EMIF.SDCKE, EMIF.SOE3, EMIF.HOLD,

EMIF.HOLDA, ECLKOUT1. EMIF.ARDY and EMIF.HOLDA do not go to a high-impedance state during reset since they are input-only

signals; they are included here simply for completeness.

(3)

High group: IACK, XF, SCL (assumes external pullup on pin), SDA (assumes external pullup on pin), UART.TX, TDO.

(4)

Z group: HRDY, HINT, DX2, DX1, DX0

(5)

Input/Output group: PGPIO[45:0], HPI.HA[15:0], HPI.HD[15:0], EMIF.D[31:0], HPI.HAS, HPI.HBIL, HCNTL1, HCNTL0, HCS, R/W,

HDS1, HDS2, NMI/WDTOUT, GPIO[7:0], TIM0, TIM1, CLKR0, CLKX0, FSR0, FSX0, CLKR1, CLKX1, FSR1, FSX1, CLKR2, CLKX2,

FSR2, FSX2, EMU0, EMU1/OFF. Signals in this group switch to input mode with reset.

(6)

Toggle group: ECLKOUT2, CLKOUT. Pins in this group toggle with a default frequency during reset.

Specifications

148

TMS320VC5502 Datasheet(PDF) 148 Page - Texas Instruments

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