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5.8

HOLD/HOLDA Timings

EMIF.HOLD

EMIF.HOLDA

EMIF Bus

(see Note A)

DSP Owns Bus

External Requestor

Owns Bus

DSP Owns Bus

5502

ECLKOUTx

EMIF Bus consists of: EMIF.CE[3:0], EMIF.BE[3:0], EMIF.D[31:0], EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE,

EMIF.AOE/SOE/SDRAS, EMIF.AWE/SWE/SDWE, EMIF.SDCKE, and EMIF.SOE3.

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-15 and Table 5-16 assume testing over recommended operating conditions (see Figure 5-21).

Table 5-15. EMIF.HOLD/HOLDA Timing Requirements

(1)

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

toh(HOLDAL-HOLDL)

Hold time, EMIF.HOLD low after EMIF.HOLDA low

(1)

E = the EMIF input clock (ECLKIN, CPU/1 clock, CPU1/2 clock, or CPU1/4 clock) period in ns for EMIF.

Table 5-16. EMIF.HOLD/HOLDA Switching Characteristics

(1) (2) (3)

VC5502-200

VC5502-300

NO.s

PARAMETER

UNIT

MIN

MAX

td(HOLDL-EMHZ)

Delay time, EMIF.HOLD low to EMIF Bus high impedance

(4)

td(EMHZ-HOLDAL)

Delay time, EMIF Bus high impedance to EMIF.HOLDA low

td(HOLDH-EMLZ)

Delay time, EMIF.HOLD high to EMIF Bus low impedance

td(EMLZ-HOLDAH)

Delay time, EMIF Bus low impedance to EMIF.HOLDA high

td(HOLDL-EKOHZ)

Delay time, EMIF.HOLD low to ECLKOUTx high impedance

(4)

td(HOLDH-EKOLZ)

Delay time, EMIF.HOLD high to ECLKOUTx low impedance

(1)

E = the EMIF input clock (ECLKIN, CPU/1 clock, CPU1/2 clock, or CPU1/4 clock) period in ns for EMIF.

(2)

EMIF Bus consists of: EMIF.CE[3:0], EMIF.BE[3:0], EMIF.D[31:0], EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE,

EMIF.AOE/SOE/SDRAS, EMIF.AWE/SWE/SDWE , EMIF.SDCKE, and EMIF.SOE3.

(3)

The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during

EMIF.HOLDA. If EKxHZ = 0, ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance

during Hold mode, as shown in Figure 5-21.

(4)

All pending EMIF transactions are allowed to complete before EMIF.HOLDA is asserted. If no bus transactions are occurring, then the

minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

Figure 5-21. EMIF.HOLD/HOLDA Timings

Specifications

147

TMS320VC5502 Datasheet(PDF) 147 Page - Texas Instruments

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