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5.14

TIM0/TIM1/WDTOUT Timings

5.14.1

TIM0/TIM1/WDTOUT Timer Pin Timings

TIM0/TIM1/WDTOUT

as Input

CLKOUT

TIM0/TIM1/WDTOUT

as Output

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-26 and Table 5-27 assume testing over recommended operating conditions(see Figure 5-28 and

Figure 5-29).

Table 5-26. TIM0/TIM1/WDTOUT Pins Configured as Timer Input Pins Timing Requirements

(1)

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

tw(TIML)

Pulse width, TIM0/TIM1/WDTOUT low

tw(TIMH)

Pulse width, TIM0/TIM1/WDTOUT high

(1)

P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2

the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

Table 5-27. TIM0/TIM1/WDTOUT Pins Configured as Timer Output Pins Switching Characteristics

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

td(COH-TIMH)

Delay time, CLKOUT high to TIM0/TIM1/WDTOUT high(1)

td(COH-TIML)

Delay time, CLKOUT high to TIM0/TIM1/WDTOUT low(1)

tw(TIM)

Pulse duration, TIM0/TIM1/WDTOUT

P(2)

(1)

In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as

CLKOUT.

(2)

P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2

the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

Figure 5-28. TIM0/TIM1/WDTOUT Timings When Configured as Timer Input Pins

Figure 5-29. TIM0/TIM1/WDTOUT Timings When Configured as Timer Output Pins

154

Specifications

TMS320VC5502 Datasheet(PDF) 154 Page - Texas Instruments

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