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5.15

Multichannel Buffered Serial Port (McBSP) Timings

5.15.1

McBSP Transmit and Receive Timings

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-31 and Table 5-32 assume testing over recommended operating conditions (see Figure 5-32 and

Figure 5-33).

Table 5-31. McBSP Transmit and Receive Timing Requirements

(1) (2)

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

M11

tc(CKRX)

Cycle time, CLKR/X

CLKR/X ext

M12

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X ext

P – 2

M13

tr(CKRX)

Rise time, CLKR/X

CLKR/X ext

M14

tf(CKRX)

Fall time, CLKR/X

CLKR/X ext

CLKR int

M15

tsu(FRH-CKRL)

Setup time, external FSR high before CLKR low

CLKR ext

CLKR int

M16

th(CKRL-FRH)

Hold time, external FSR high after CLKR low

CLKR ext

CLKR int

M17

tsu(DRV-CKRL)

Setup time, DR valid before CLKR low

CLKR ext

CLKR int

M18

th(CKRL-DRV)

Hold time, DR valid after CLKR low

CLKR ext

CLKX int

M19

tsu(FXH-CKXL)

Setup time, external FSX high before CLKX low

CLKX ext

CLKX int

M20

th(CKXL-FXH)

Hold time, external FSX high after CLKX low

CLKX ext

(1)

Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that

signal are also inverted.

(2)

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2

the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

Specifications

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TMS320VC5502 Datasheet(PDF) 158 Page - Texas Instruments

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