TMS320VC5502 datasheet(162/189 Pages) TI

162 / 189 page

www.ti.com

5.15.3

McBSP as SPI Master or Slave Timings

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-35 to Table 5-42 assume testing over recommended operating conditions (see Figure 5-35 through

Figure 5-38).

Table 5-35. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)

(1) (2) (3)

VC5502-200

VC5502-300

NO.

UNIT

MASTER

SLAVE

MIN

MAX

MIN

MAX

M30

tsu(DRV-CKXL)

Setup time, DR valid before CLKX low

0 – 5P

M31

th(CKXL-DRV)

Hold time, DR valid after CLKX low

9 + 6P

M32

tsu(FXL-CKXH)

Setup time, FSX low before CLKX high

M33

tc(CKX)

Cycle time, CLKX

16P

(1)

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2

the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)

McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number

SPRU592).

Table 5-36. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)

(1) (2) (3) (4)

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MASTER

SLAVE

MIN

MAX

MIN

MAX

M24

td(CKXL-FXL)

Delay time, CLKX low to FSX low(5)

T – 2

T + 6

M25

td(FXL-CKXH)

Delay time, FSX low to CLKX high(6)

C – 6

C + 4

M26

td(CKXH-DXV)

Delay time, CLKX high to DX valid

–4

Disable time, DX high impedance following last data bit from

M27

tdis(CKXL-DXHZ)

C – 2

C +10

CLKX low

Disable time, DX high impedance following last data bit from

M28

tdis(FXH-DXHZ)

2P + 4

4P + 10

FSX high

M29

td(FXL-DXV)

Delay time, FSX low to DX valid

2P + 4

4P + 10

(1)

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2

the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)

McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number

SPRU592).

(4)

T = BCLKX period = (1 + CLKGDV) * 2P

C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even

(5)

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on

FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

(6)

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master

clock (CLKX).

Specifications

162

TMS320VC5502 Datasheet(PDF) 162 Page - Texas Instruments

TMS320VC5502 Datasheet(HTML) 162 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL