TMS320VC5502 datasheet(159/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-32. McBSP Transmit and Receive Switching Characteristics

(1) (2)

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

tc(CKRX)

Cycle time, CLKR/X

CLKR/X int

tw(CKRXH)

Pulse duration, CLKR/X high

CLKR/X int

D – 1(3)

D + 1(3)

tw(CKRXL)

Pulse duration, CLKR/X low

CLKR/X int

C – 1(3)

C + 1(3)

CLKR int

–2

td(CKRH-FRV)

Delay time, CLKR high to internal FSR valid

CLKR ext

CLKX int

–2

td(CKXH-FXV)

Delay time, CLKX high to internal FSX valid

CLKX ext

CLKX int

–5

Disable time, CLKX high to DX high impedance

tdis(CKXH-DXHZ)

following last data bit

CLKX ext

CLKX int

Delay time, CLKX high to DX valid.

This applies to all bits except the first bit transmitted.

CLKX ext

CLKX int

Delay time, CLKX high to DX valid(4)

td(CKXH-DXV)

DXENA = 0

CLKX ext

Only applies to first bit transmitted when

in Data Delay 1 or 2 (XDATDLY=01b or

CLKX int

2P + 2

DXENA = 1

10b) modes

CLKX ext

2P + 8

CLKX int

Enable time, CLKX high to DX driven(4)

DXENA = 0

CLKX ext

Only applies to first bit transmitted when

ten(CKXH-DX)

in Data Delay 1 or 2 (XDATDLY=01b or

CLKX int

DXENA = 1

10b) modes

CLKX ext

2P + 6

FSX int

DXENA = 0

Delay time, FSX high to DX valid(4)

FSX ext

td(FXH-DXV)

Only applies to first bit transmitted when

FSX int

2P + 2

in Data Delay 0 (XDATDLY=00b) mode.

DXENA = 1

FSX ext

2P + 7

FSX int

DXENA = 0

Enable time, FSX high to DX driven(4)

FSX ext

M10

ten(FXH-DX)

Only applies to first bit transmitted when

FSX int

in Data Delay 0 (XDATDLY=00b) mode

DXENA = 1

FSX ext

P + 6

(1)

Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that

signal are also inverted.

(2)

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2

the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)

T = CLKRX period = (1 + CLKGDV) * P

C = CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even

D = CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even

(4)

See the TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature

number SPRU592) for a description of the DX enable (DXENA) and data delay features of the McBSP.

159

Specifications

TMS320VC5502 Datasheet(PDF) 159 Page - Texas Instruments

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