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5.16

Host-Port Interface Timings

5.16.1

HPI Read and Write Timings

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-43 and Table 5-44 assume testing over recommended operating conditions (see Figure 5-39 through

Figure 5-44).

Table 5-43. HPI Read and Write Timing Requirements

(1) (2) (3)

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

tsu(HASL-DSL)

Setup time, HPI.HAS low before DS falling edge

H10

th(DSL-HASL)

Hold time, HPI.HAS low after DS falling edge

H11

tsu(HAD-HASL)

Setup time, HAD valid before HPI.HAS falling edge

H12

th(HASL-HAD)

Hold time, HAD valid after HPI.HAS falling edge

H13

tw(DSL)

Pulse duration, DS low

H14

tw(DSH)

Pulse duration, DS high

H15

tsu(HAD-DSL)

Setup time, HAD valid before DS falling edge

H16

th(DSL-HAD)

Hold time, HAD valid after DS falling edge

H17

tsu(HD-DSH)

Setup time, HD valid before DS rising edge

H18

th(DSH-HD)

Hold time, HD valid after DS rising edge

H37

tsu(HCSL-DSL)

Setup time, HCS low before DS falling edge

H38

th(HRDYH-DSL)

Hold time, DS low after HRDY rising edge

(1)

P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2

the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(2)

DS refers to logical OR of HCS, HDS1, and HDS2. HD refers to HPI Data Bus. HDS refers to HDS1 or HDS2. HAD refers to HCNTL0,

HCNTL1, HPI.HBIL, and HR/W.

(3)

A host must not initiate transfer requests until the HPI has been brought out of reset, see Section 3.8, Host-Port Interface (HPI), for

more details.

169

Specifications

TMS320VC5502 Datasheet(PDF) 169 Page - Texas Instruments

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