TMS320VC5502 datasheet(167/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-41. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)

(1) (2) (3)

VC5502-200

VC5502-300

NO.

UNIT

MASTER

SLAVE

MIN

MAX

MIN

MAX

M58

tsu(DRV-CKXL)

Setup time, DR valid before CLKX low

0 – 5P

M59

th(CKXL-DRV)

Hold time, DR valid after CLKX low

9 + 6P

M60

tsu(FXL-CKXL)

Setup time, FSX low before CLKX low

M61

tc(CKX)

Cycle time, CLKX

16P

(1)

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2

the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)

McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number

SPRU592).

Table 5-42. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)

(1) (2) (3) (4)

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MASTER

SLAVE

MIN

MAX

MIN

MAX

M53

td(CKXH-FXL)

Delay time, CLKX high to FSX low(5)

D – 2

D + 6

M54

td(FXL-CKXL)

Delay time, FSX low to CLKX low(6)

T – 6

T + 4

M55

td(CKXH-DXV)

Delay time, CLKX high to DX valid

–4

Disable time, DX high impedance following last

M56

tdis(CKXH-DXHZ)

–2

3P + 4

4P + 18

data bit from CLKX high

M57

td(FXL-DXV)

Delay time, FSX low to DX valid

C – 2

C + 10

2P – 4

4P + 10

(1)

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)

P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2

the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)

McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number

SPRU592).

(4)

T = CLKX period = (1 + CLKGDV) * P

C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even

D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even

(5)

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on

FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

(6)

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master

clock (CLKX).

167

Specifications

TMS320VC5502 Datasheet(PDF) 167 Page - Texas Instruments

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