MCP19124 datasheet(181/236 Pages) MICROCHIP

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DS20005619A-page 181

MCP19124/5

28.5.6

I2C MASTER MODE

TRANSMISSION

Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSPBUF register. This action will

set the Buffer Full (BF) flag bit and allow the Baud Rate

Generator to begin counting and start the next

transmission. Each bit of address/data will be shifted

out onto the SDA pin after the falling edge of SCL is

asserted. SCL is held low for one Baud Rate Generator

rollover count (TBRG). Data should be valid before SCL

is released high. When the SCL pin is released high, it

is held that way for TBRG. The data on the SDA pin must

remain stable for that duration and some hold time after

the next falling edge of SCL. After the 8th bit is shifted

out (the falling edge of the 8th clock), the BF flag is

cleared and the master releases the SDA. This allows

the slave device being addressed to respond with an

ACK bit during the 9th bit time if an address match

occurred or if data was received properly. The status of

ACK is written into the ACKSTAT bit on the rising edge

of the 9th clock. If the master receives an Acknowledge,

the Acknowledge Status bit (ACKSTAT) is cleared. If

not, the bit is set. After the 9th clock, the SSPIF bit is set

and the master clock (Baud Rate Generator) is

suspended until the next data byte is loaded into the

SSPBUF, leaving SCL low and SDA unchanged

(Figure 28-20).

After the write to the SSPBUF, each bit of the address

will be shifted out on the falling edge of SCL until all

seven address bits and the R/W bit are completed. On

the falling edge of the 8th clock, the master will release

the SDA pin, allowing the slave to respond with an

Acknowledge. On the falling edge of the 9th clock, the

master will sample the SDA pin to see if the address

was recognized by a slave. The status of the ACK bit is

loaded into the ACKSTAT status bit in the SSPCON2

transmission of the address, the SSPIF is set, the BF

flag is cleared and the Baud Rate Generator is turned

off until another write to the SSPBUF takes place,

holding SCL low and allowing SDA to float.

28.5.6.1

BF Status Flag

In Transmit mode, the BF bit in the SSPSTAT register

is set when the CPU writes to SSPBUF and is cleared

when all 8 bits are shifted out.

28.5.6.2

WCOL Status Flag

If the user writes the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL is set and the contents of the

buffer are unchanged (the write does not occur).

WCOL must be cleared by software before the next

transmission.

28.5.6.3

ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit in the SSPCON2

Acknowledge (ACK = 0) and is set when the slave

does not Acknowledge (ACK = 1). A slave sends an

Acknowledge when it has recognized its address

(including a general call) or when the slave has

properly received its data.

28.5.6.4

Typical Transmit Sequence:

The user generates a Start condition by setting

the SEN bit in the SSPCON2 register.

SSPIF is set by hardware on completion of the

Start.

SSPIF is cleared by software.

The MSSP module will wait the required start

time before any other operation takes place.

The user loads the SSPBUF with the slave

address to transmit.

Address is shifted out the SDA pin until all 8 bits

are transmitted. Transmission begins as soon

as SSPBUF is written to.

The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit in the SSPCON2 register.

The MSSP module generates an interrupt at the

end of the 9th clock cycle by setting the SSPIF

bit.

The user loads the SSPBUF with 8 bits of data.

10. Data is shifted out the SDA pin until all 8 bits are

transmitted.

11. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit in the SSPCON2 register.

12. Steps 8-11 are repeated for all transmitted data

bytes.

13. The user generates a Stop or Restart condition

by setting the PEN or RSEN bits in the

SSPCON2 register. Interrupt is generated once

the Stop/Restart condition is complete.

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