MCP19124 datasheet(183/236 Pages) MICROCHIP

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 2016 Microchip Technology Inc.

DS20005619A-page 183

MCP19124/5

28.5.7

I2C MASTER MODE RECEPTION

Master mode reception is enabled by programming the

Receive Enable (RCEN) bit in the SSPCON2 register.

The Baud Rate Generator begins counting and, upon

each rollover, the state of the SCL pin changes

(high-to-low/low-to-high) and data is shifted into the

SSPSR. After the falling edge of the 8th clock, the

receive enable flag is automatically cleared, the

contents of the SSPSR are loaded into the SSPBUF,

the BF flag bit is set, the SSPIF flag bit is set and the

Baud Rate Generator is suspended from counting,

holding SCL low. The MSSP is now in idle state

awaiting the next command. When the buffer is read by

the CPU, the BF flag bit is automatically cleared. The

user can then send an Acknowledge bit at the end of

reception by setting the Acknowledge Sequence

Enable (ACKEN) bit in the SSPCON2 register.

28.5.7.1

BF Status Flag

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

28.5.7.2

SSPOV Status Flag

In receive operation, the SSPOV bit is set when 8 bits

are received into the SSPSR and the BF flag bit is

already set from a previous reception.

28.5.7.3

WCOL Status Flag

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), the WCOL bit is set and the contents of the buffer

are unchanged (the write does not occur).

28.5.7.4

Typical Receive Sequence

The user generates a Start condition by setting

the SEN bit in the SSPCON2 register.

SSPIF is set by hardware on completion of the

Start.

SSPIF is cleared by software.

User writes SSPBUF with the 7-bit slave

address to transmit and sets the R/W bit.

Address is shifted out the SDA pin until all 8 bits

are transmitted. Transmission begins as soon

as SSPBUF is written to.

The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit in the SSPCON2 register.

The MSSP module generates an interrupt at the

end of the 9th clock cycle by setting the SSPIF

bit.

User sets the RCEN bit in the SSPCON2 register

and the Master clocks in a byte from the slave.

After the 8th falling edge of SCL, SSPIF and BF

are set.

10. Master clears SSPIF and reads the received

byte from SSPUF, then clears BF.

11. Master sets ACK value sent to slave in ACKDT

bit in the SSPCON2 register and initiates the

ACK by setting the ACKEN bit.

12. Masters ACK is clocked out to the Slave and

SSPIF is set.

13. The user clears SSPIF.

14. Steps 8-13 are repeated for each received byte

from the slave.

15. Master sends a not ACK or Stop to end

communication.

Note:

The MSSP module must be in an idle

state before the RCEN bit is set or the

RCEN bit will be disregarded.

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