MCP19124 datasheet(185/236 Pages) MICROCHIP

185 / 236 page

 2016 Microchip Technology Inc.

DS20005619A-page 185

MCP19124/5

28.5.8

ACKNOWLEDGE SEQUENCE

TIMING

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable (ACKEN) bit in the

SSPCON2 register. When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the user wishes to

generate an Acknowledge, then the ACKDT bit should

be cleared. If not, the user should set the ACKDT bit

before starting an Acknowledge sequence. The Baud

Rate Generator then counts for one rollover period

(TBRG) and the SCL pin is deasserted (pulled high).

When the SCL pin is sampled high (clock arbitration),

the Baud Rate Generator counts for TBRG. The SCL pin

is then pulled low. Following this, the ACKEN bit is

automatically cleared, the Baud Rate Generator is

turned off and the MSSP module then goes into Idle

mode (Figure 28-22).

28.5.8.1

WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, WCOL is set and the contents

of the buffer are unchanged (the write does not occur).

28.5.9

STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN, in the SSPCON2 register. At the end of a

receive/transmit, the SCL line is held low after the

falling edge of the 9th clock. When the PEN bit is set,

the master will assert the SDA line low. When the SDA

line is sampled low, the Baud Rate Generator is

reloaded and counts down to ‘0’. When the Baud Rate

Generator times out, the SCL pin will be brought high

and then, one TBRG (Baud Rate Generator rollover

count) later, the SDA pin will be deasserted. When the

SDA pin is sampled high while SCL is high, the P bit in

the SSPSTAT register, is set. A TBRG later, the PEN bit

is cleared and the SSPIF bit is set (Figure 28-23).

28.5.9.1

WCOL Status Flag

If the user writes the SSPBUF when a Stop sequence

is in progress, the WCOL bit is set and the contents of

the buffer are unchanged (the write does not occur).

FIGURE 28-22:

ACKNOWLEDGE SEQUENCE WAVEFORM

FIGURE 28-23:

STOP CONDITION RECEIVE OR TRANSMIT MODE

SDA

SCL

ACKEN automatically cleared

TBRG

SSPIF

ACK

Acknowledge sequence starts here,

write to SSPCON2

ACKEN = 1, ACKDT = 0

SSPIF set at the end

of receive

Cleared by

software

Cleared by

software

SSPIF set at the end

of Acknowledge sequence

Note:

TBRG = one Baud Rate Generator period.

SCL

SDA

SCL brought high after TBRG

TBRG

ACK

TBRG

Write to SSPCON2,

set PEN

Falling edge of 9th clock

SCL = 1 for TBRG, followed by SDA = 1 for TBRG

after SDA sampled high. P bit (SSPSTAT4) is set.

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

Note:

TBRG = one Baud Rate Generator period.

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