PM6344 datasheet(194/256 Pages) PMC

194 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

181

range between 4 bit/s and 20 kbit/s. RDLSIG[x] is generated on the falling edge

of RDLCLK[x]. For the diagram shown above, the SRSMFP and SRCMFP

is valid only if the RCLKOSEL bit is set to logic 0.

Figure 11

- TS16 Transmit Datalink Interface

TDLCLK[x]

TDLSIG[x]

TDP/TDD[x]

TDN[x]

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

567

1011 12 1314 1516

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Time Slots

BTPCM[x] 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

567

1011 1213 14 1516 17

CCS data collected over 32 timeslots

and inserted into TS16

When Common Channel Signaling (CCS) data sourced from TDLSIG[x] is

selected (DLEN=1, SIGEN=0 and TXDMASIG=0), TDLCLK[x] is active,

producing one cycle every 4 time slots, aligned to the incoming BTPCM[x]. The

data on TDLSIG[x] is sampled on the rising edge of TDLCLK[x] and put directly

into TS16 on the outgoing data stream.

Figure 12

- TS0 Transmit Datalink Interface

BTCLK[x]

BTPCM[x]

Timeslot 31

7 8

1 2 3 45

1 2 3 4 5

6 781 2 3 4

12 3 45 6 78

NFAS, Timeslot 0

FAS, Timeslot 0

TDLCLK[x]

TDLSIG[x]

Don't Care

4 5 678

When the TS0 maintenance datalink is active (DLEN=0 or SIGEN=1,

TXDMASIG=0, at least one TXSAxEN bit is a logic 1), the data presented on

TDLSIG[x] is inserted into the National Use bits of the NFAS frames. A clock

pulse is generated on TDLCLK[x] for each National Use bit on TDLSIG[x] which

has the associated enable (TXSAxEN, x=4 to 8) set to logic 1. If the enable is

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