PM6344 datasheet(197/256 Pages) PMC

197 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

184

Figure 16

- ELSTBYP=1, SRSMFP=1, SRCMFP=1, BRXSMFP=1,

BRXCMFP=0

12 3456 78

AB C D

12 3456 78123456 78

ABC D

123456 7812 3 456 78

Timeslot 31

Timeslot 0

Timeslot 1

Timeslot 31

Timeslot 0

RCLKO[x]

BRFPO[x]

BRPCM[x]

BRSIG[x]

RFP[x]

Undefined

ABC D

Undefined

The Receive Backplane is configured to generate single-rail formatted data with

frame alignment indication and with the ELST bypassed (ELSTBYP=1). The

Receive Options register is programmed to SRSMFP=1 and SRCMFP=1, the

Receive Backplane Options register is programmed to BRXSMFP=1 and

BRXCMFP=0. In this case, the backplane output signals are timed off of the

output clock RCLKO[x] instead of the input clock BRCLK. RFP marks (though

offset by 3 bits) the start of each signaling multiframe, and the start of each CRC

multiframe.

Figure 17

- Receive Channel Interface

RCLKO[x]

RDLSIG[x] 1 2 34567 8 1 2 3456 7 8 1 2 3456 78

1 2 3456 7 8

12 3456 78

Timeslot 31

Timeslot 0

Timeslot 1

Timeslot 31

Timeslot 0

RFP[x]

RDLCLK[x]

Don't Care

The RFRACE1 bit in the Datalink Options register is set to logic 1. The CH[1]

and CH[31] register bits in the Channel Select registers are set to logic 1 and the

CH[0] register bit is set to logic 0. Channels 1 and 31 are presented on

RDLSIG[x]. RDLCLK[x] is gapped so that it is only active for the channels with

the associated CH[x] bit set. As shown here, the SRCMFP and SRSMFP bits in

the Receive Options register are set to logic 0.

PM6344 Datasheet(PDF) 197 Page - PMC-Sierra, Inc

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