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PM6344 Datasheet(PDF) 200 Page - PMC-Sierra, Inc |
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PM6344 Datasheet(HTML) 200 Page - PMC-Sierra, Inc |
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200 / 256 page  STANDARD PRODUCT PMC-Sierra, Inc. PM6344 EQUAD PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER 187 The Receive Backplane is configured to generate bit interleaved 16.384MHz data. PCM and signaling for all four receivers are presented on a single pin, MRD. The superscripts represent the index of the particular E1 stream. The Receive Backplane Options register for each receiver is programmed to BRX2RAIL=0 and the MENB input is low. The preceding figure shows the expected outputs if all four E1 framers are outputting NFAS frames. If the BRPTYPE bit in the Backplane Parity Configuration and Status register is set to logic 1, the backplane receive parity is enabled. The International bit (Si bit) of the PCM data stream in each frame is replaced by the parity value calculated over the previous frame (not counting the parity bit of the previous frame). The parity bit of each SIG stream follows the parity bit of the PCM data stream. |
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