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PM6344 Datasheet(PDF) 227 Page - PMC-Sierra, Inc

Part # PM6344
Description  QUADRUPLE E1 FRAMER
PDF  256 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM6344 Datasheet(HTML) 227 Page - PMC-Sierra, Inc

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STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
214
The method of accessing the indirect registers within the SIGX functional
block is the same as that explained in the EQUAD databook section entitled
"Using the Per-Channel Serial Controllers."
The SIGX should be configured as follows:
a) Set the IND bit in quadrant 1 register 040H (0C0H, 140H or 1C0H for
quadrants 2, 3 or 4) to a logic one. This will enable accesses to the SIGX
indirect registers.
b) Program the SIGX indirect registers such that, for timeslots 1-15 and 17-
31 the per-timeslot Configuration and Signaling Trunk Conditioning data
registers contain 10H. This will configure the SIGX to debounce the
received signaling states as explained in the RDEBE bit description.
c) Set the PCCE bit in register 040H (0C0H, 140H, 1C0H) to a logic one.
This will enable the SIGX to perform the functions configured in step (b)
above.
5) Configure for Diagnostic Digital Loopback. To accomplish this:
a) Program quadrant 1 Register 00AH (08AH, 10AH or 18AH for quadrants
2, 3 or 4) to 04H. This will enable the Diagnostic Digital Loopback mode of
the EQUAD which internally loops back the transmit data to the receive
circuitry. This mode is sometimes called a "local" loopback.
b) Program Register 10H (090H, 110H, 190H) to default value of 00H and
Register 44H (0C4H, 144H, 1C4H) to 70H for CRC generation. Program
register 20H to 80H to enable CRC framing. This will enable the receiver
to accept the HDB3-encoded signal sourced by the transmitter.
6) Disable Elastic Store.
This can be done by bypassing elastic store. To do this, program Register
00H (080H, 100H, 180H) to a value of 20H.
7) Wait until the FRMR functional block is solidly in-frame.
This can be determined by polling the OOF, OOSMF and OOCMF bits in
Register 026H (0A6H, 126H, 1A6H) and the OOFI, OOSMFI and OOCMFI
bits in Register 024H (0A4H, 124H, 1A4H). When the OOF, OOSMF and
OOCMF bits are low (logic zero) for two consecutive polls, and the OOFI,
OOSMFI and OOCMFI bits are low (logic zero) on the second consecutive
poll, then you can assume that the FRMR functional block of the current
quadrant of the EQUAD has found a stable frame alignment pattern.



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