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VDP3108 Datasheet(PDF) 20 Page - Micronas

Part # VDP3108
Description  Single-Chip Video Processor
PDF  61 Pages
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Manufacturer  MICRONAS [Micronas]
Direct Link  http://www.micronas.com
Logo MICRONAS - Micronas

VDP3108 Datasheet(HTML) 20 Page - Micronas

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VDP 3108
ADVANCE INFORMATION
MICRONAS INTERMETALL
20
2.6.1. Video Sync Processing
Fig. 2–25 shows a block diagram of the front end sync
processing. To extract the sync information from the
video signal, a linear phase lowpass filter eliminates all
noise and video contents above one MHz. The sync is
separated by a slicer, the sync phase is measured. A
variable window can be selected to improve the noise
immunity of the slicer. The phase comparator measures
the falling edge of sync as well as the integrated sync
pulse.
The sync phase error is filtered by a phase locked loop
that is computed by the FP. All timing in the front end is
derived from a counter that is part of this PLL and it thus
counts synchronously to the video signal.
A separate hardware block measures the signal back
porch and also allows to gather maximum/minimum of
the video signal. This information is processed by the FP
and used for of gain control and clamping.
For vertical sync separation the sliced video signal is in-
tegrated. The FP uses the integrator value to derive ver-
tical sync and field information.
The information extracted by the video sync processing
is multiplexed onto the hardware front sync signal (FSY)
and is distributed to the rest of the video processing sys-
tem. The format of the front sync signal is given in fig.
2–26.
The data for the vertical deflection, the sawtooth and the
East-West correction signal is calculated by the FP. The
data is buffered in a FIFO and transferred to the back
end by a single wire interface.
.
phase
comparator
&
lowpass
counter
frontend
timing
FSY
lowpass
1 MHz
&
syncslicer
horizontal
sync
separation
vertical
sync
separation
FIFO
Sawtooth
video
input
skew
front
sync
generator
vertical
serial
data
VDATA
sawtooth
E/W
Parabola
Calculation
clamping, colorkey, FIFO_write
PLL1
clamp &
signal
meas.
Fig. 2–25: Sync separation block diagram
v blank
even field
F1
F2
F3
F4
F5
(not in scale)
input
analog
video
FSY
F1
Parity
V:
Vert. blanking
0 = off
1 = on
F:
Field #
0 = field 1
1 = field 2
Fig. 2–26: Front sync format
F0
skew
MSB
skew
LSB
not
used
FV
F0, F2..F5 reserved



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