LAN91C111 datasheet(55/125 Pages) MICROCHIP

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DS00002276A-page 55

LAN91C111

8.18

Bank 2 - FIFO Ports Register

This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet num-

bers to be processed by the interrupt service routines are read from this register.

REMPTY - No receive packets queued in the RX FIFO. For polling purposes, uses the RCV_INT bit in the Interrupt Sta-

tus Register.

TOP OF RX FIFO PACKET NUMBER - Packet number presently at the output of the RX FIFO. Only valid if REMPTY

is clear. The packet is removed from the RX FIFO using MMU Commands 3) or 4).

TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the Interrupt Status

TX FIFO PACKET NUMBER - Packet number presently at the output of the TX FIFO. Only valid if TEMPTY is clear. The

packet is removed when a TX INT acknowledge is issued.

OFFSET

NAME

TYPE

SYMBOL

FIFO PORTS REGISTER

READ ONLY

FIFO

HIGH

BYTE

REMPTY

Reserved

RX FIFO PACKET NUMBER

100

000

LOW

BYTE

TEMPTY

Reserved

TX FIFO PACKET NUMBER

100

000

Note:

For software compatibility with future versions, the value read from each FIFO register is intended to be

written into the PNR as is, without masking higher bits (provided TEMPTY and REMPTY = 0 respectively).

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