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TMS320C51 Datasheet(PDF) 60 Page - Texas Instruments |
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TMS320C51 Datasheet(HTML) 60 Page - Texas Instruments |
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60 / 87 page  TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MEMORY AND PARALLEL I/O INTERFACE WRITE switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (’320C5x only) (see Figure 15) PARAMETER ’320C5x-40 ’320C5x-57 ’320C5x-80 ’320C5x-100 UNIT PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX UNIT tsu(AV-WEL) Setup time, address valid before WE low† H–5‡ H–5‡ H–4‡ H–3‡ ns tsu(WDV-WEH) Setup time, write data valid before WE high 2H – 20 2H§¶ 2H – 20 2H§¶ 2H – 14 2H§¶ 2H – 14 2H§¶ ns th(WEH-AV) Hold time, address valid after WE high† H–10‡ H–10‡ H–7‡ H–7‡ ns th(WEH-WDV) Hold time, write data valid after WE high H–5 H+10§ H–5 H+10§ H–4 H+7§ H–4 H+7§ ns tw(WEL) Pulse duration, WE low§¶ 2H – 2 2H + 2§ 2H – 2 2H + 2§ 2H – 2 2H + 2 2H – 2 2H + 2 ns tw(WEH) Pulse duration, WE high§ 2H – 2 2H – 2 2H – 2 2H – 2 ns td(CO-ST) Delay time, CLKOUT1 to STRB rising or falling edge§ –1 3 –2 2 –2 2 –2 2 ns td(CO-WE) Delay time, CLKOUT1 to WE rising or falling edge§ 0 4 –1 3 –1 3 –1 3 ns td(WEH-RDL) Delay time, WE high to RD low 3H – 10 3H – 10 3H – 7 3H – 7 ns ten(WEL-BUd) Enable time, WE low to data bus driven –5§ –5§ –4§ –4§ ns switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (’320LC5x only) (see Figure 15) PARAMETER ’320LC5x-40 ’320LC5x-50 ’320LC5x-80 UNIT MIN MAX MIN MAX tsu(AV-WEL) Setup time, address valid before WE low† H–7‡ H–4‡ ns tsu(WDV-WEH) Setup time, write data valid before WE high# 2H – 20 2H§¶ 2H – 14 2H§¶ ns th(WEH-AV) Hold time, address valid after WE high† H–10‡ H–7‡ ns th(WEH-WDV) Hold time, write data valid after WE high H–5 H+10§ H–4 H+7§ ns tw(WEL) Pulse duration, WE low¶§ 2H – 4 2H + 2 2H – 4 2H + 2 ns tw(WEH) Pulse duration, WE high¶ 2H – 2 2H – 2 ns td(WEH-RDL) Delay time, WE high to RD low 3H – 10 3H – 7 ns td(CO-ST) Delay time, CLKOUT1 to STRB rising or falling edge¶ 0 4 –2 2 ns td(CO-WE) Delay time, CLKOUT1 to WE rising or falling edge¶ 0 4 –1 3 ns ten(WE-BUd) Enable time, WE to data bus driven –5§ –4§ ns † A0 – A15, PS, DS, IS, R / W, and BR timings are all included in timings referenced as address. ‡ See Figure 16 for address bus timing variation with load capacitance. § Values derived from characterization data and not tested ¶ This value holds true for zero wait states or one software wait state only. # STRB and WE edges are 0 – 4 ns from CLKOUT1 edges on writes. Rising and falling edges of these signals track each other; tolerance of resulting pulsewidths is ±2 ns, not ±4 ns. |
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