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TMS320C51 Datasheet(PDF) 64 Page - Texas Instruments

Part # TMS320C51
Description  DIGITAL SIGNAL PROCESSORS
PDF  87 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320C51 Datasheet(HTML) 64 Page - Texas Instruments

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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
64
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
RESET, INTERRUPT, AND BIO
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = 0.5tc(CO)] (see Figure 19)
’320C5x-40
’320C5x-57
’320LC5x-40
’320LC5x-50
’320C5x-80
’320C5x-100
’320LC5x-80
UNIT
MIN
MAX
MIN
MAX
tsu(IN-COL)
Setup time, INT1–INT4, NMI before CLKOUT1 low †
15
10
ns
tsu(RS-COL)
Setup time, RS before CLKOUT1 low
15
2H – 5‡
10
2H – 5‡
ns
tsu(RS-CIL)
Setup time, RS before X2/CLKIN low
10
7
ns
tsu(BI-COL)
Setup time, BIO before CLKOUT1 low
15
10
ns
th(COL-IN)
Hold time, INT1–INT4, NMI after CLKOUT1 low †
0
0
ns
th(COL-BI)
Hold time, BIO after CLKOUT1 low
0
0
ns
tw(INL)SYN
Pulse duration, INT1–INT4, NMI low, synchronous
4H + 15§
4H + 10§
ns
tw(INH)SYN
Pulse duration, INT1–INT4, NMI high, synchronous
2H + 15§
2H + 10§
ns
tw(INL)ASY
Pulse duration, INT1–INT4, NMI low, asynchronous ‡
6H + 15§
6H + 10§
ns
tw(INH)ASY
Pulse duration, INT1–INT4, NMI high, asynchronous ‡
4H + 15§
4H + 10§
ns
tw(RSL)
Pulse duration, RS low
12H
12H
ns
tw(BIL)SYN
Pulse duration, BIO low, synchronous
15
10
ns
tw(BIL)ASY
Pulse duration, BIO low, asynchronous ‡
H+15
H+10
ns
td(RSH)
Delay time, RS high to reset vector fetch
34H
34H
ns
† These parameters must be met to use the synchronous timings. Both reset and the interrupts can operate asynchronously. The pulse durations
require an extra half-cycle to ensure internal synchronization.
‡ Values derived from characterization data and not tested
§ If in IDLE2, add 4H to these timings.
BIO
RS
X2/CLKIN
tsu(RS-CIL)
tsu(BI-COL)
tsu(IN-COL)
th(COL-BI)
A0 – A15
tsu(IN-COL)
th(COL-IN)
tw(BIL)SYN
td(RSH)
CLKOUT1
tw(RSL)
INT4 – INT1
tw(INH)SYN
tw(INL)SYN
tsu(RS-COL)
Figure 19. Reset, Interrupt, and BIO Timings



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