TMS320C51 datasheet(69/87 Pages) TI

69 / 87 page

TMS320C5x, TMS320LC5x

DIGITAL SIGNAL PROCESSORS

SPRS030A – APRIL 1995 – REVISED APRIL 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SERIAL-PORT RECEIVE TIMING

timing requirements over recommended ranges of supply voltage and operating ambient-air

temperature [H = 0.5tc(CO)] (see Figure 22)

’320C5x-40

’320C5x-57

’320LC5x-40

’320LC5x-50

’320C5x-80

’320LC5x-80

’320C5x-100

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tc(SCK)

Cycle time, serial-port clock

5.2H†

‡

5.2H†

‡

5.2H†

‡

tf(SCK)

Fall time, serial-port clock

8§

6§

tr(SCK)

Rise time, serial-port clock

8§

6§

tw(SCK)

Pulse duration, serial-port clock low / high

2.1H†

tsu(FS-CK)

Setup time, FSR before CLKR falling edge

tsu(DR-CK)

Setup time, DR before CLKR falling edge

th(CK-FS)

Hold time, FSR after CLKR falling edge

th(CK-DR)

Hold time, DR valid after CLKR falling edge

† Values ensured by design but not tested

‡ The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.

§ Values derived from characterization data and not tested

Bit

FSR

CLKR

8/16

7/15

tsu(DR-CK)

tsu(FS-CK)

th(CK-FS)

tw(SCK)

tr(SCK)

tf(SCK)

tw(SCK)

th(CK-DR)

tc(SCK)

Figure 22. Serial-Port Receive Timing

TMS320C51 Datasheet(PDF) 69 Page - Texas Instruments

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