TMS320C51 datasheet(29/87 Pages) TI

29 / 87 page

TMS320C5x, TMS320LC5x

DIGITAL SIGNAL PROCESSORS

SPRS030A – APRIL 1995 – REVISED APRIL 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

interrupts and subroutines

The ’C5x implements four general-purpose interrupts, INT4 – INT1, along with reset (RS) and the nonmaskable

interrupt (NMI) which are available for external devices to request the attention of the processor. Internal

interrupts are generated by the serial port (RINT and XINT), by the timer (TINT), and by the software-interrupt

(TRAP, INTR, and NMI) instructions. Interrupts are prioritized with RS having the highest priority, followed by

NMI, and INT4 having the lowest priority. Additionally, any interrupt except RS and NMI can be masked

individually with a dedicated bit in the interrupt mask register (IMR) and can be cleared, set, or tested using its

own dedicated bit in the interrupt flag register (IFR). The reset and NMI functions are not maskable.

All interrupt vector locations are on two-word boundaries so that branch instructions can be accommodated in

those locations. While normally located at program memory address 0, the interrupt vectors can be remapped

to the beginning of any 2K-word page in program memory by modifying the contents of the interrupt vector

pointer (IPTR) located in the PMST status register.

A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle

instruction, the interrupt is not processed until the instruction completes execution. This mechanism applies to

instructions that are repeated (using the RPT instruction) and to instructions that become multicycle because

of wait states.

Each time an interrupt is serviced or a subroutine is entered, the PC is pushed onto an internal hardware stack,

providing a mechanism for returning to the previous context. The stack contains eight locations, allowing

interrupts or subroutines to be nested up to eight levels deep.

In addition to the eight-level hardware PC stack, eleven key CPU registers are equipped with an associated

single-level stack or shadow register into which the registers’ contents are saved upon servicing an interrupt.

The contents are restored into their particular CPU registers once a return-from-interrupt instruction (RETE or

RETI) is executed. The registers that have the shadow-register feature include the ACC and buffer, product

sophisticated context save and restore operations to be handled automatically in cases where nested interrupts

are not required or if interrupt servicing is performed serially.

power-down modes

The ’C5x implements several power-down modes in which the ’C5x core enters a dormant state and dissipates

considerably less power. A power-down mode is invoked either by executing the IDLE / IDLE2 instructions or

by driving the HOLD input low. When the HOLD signal initiates the power-down mode, on-chip peripherals

continue to operate; this power-down mode is terminated when HOLD goes inactive.

While the ’C5x is in a power-down mode, all internal contents are maintained; this allows operation to continue

unaltered when the power-down mode is terminated. All CPU activities are halted when the IDLE instruction

is executed, but the CLKOUT1 pin remains active. The peripheral circuits continue to operate, allowing

peripherals such as serial ports and timers to take the CPU out of its powered-down state. A power-down mode,

when initiated by an IDLE instruction, is terminated upon receipt of an interrupt.

The IDLE2 instruction is used for a complete shutdown of the core CPU as well as all on-chip peripherals. In

IDLE2, the power is reduced significantly because the entire device is stopped. The power-down mode is

terminated by activating any of the external interrupt pins (RS, NMI, INT1, INT2, INT3, and INT4) for at least

five machine cycles.

bus-keeper circuitry (TMS320LC56 /’C57S/’LC57 )

The TMS320LC56 /’C57S /’LC57 devices provide built-in bus keeper circuitry which holds the last state driven

on the data bus by either the DSP or an external device after the bus is no longer being driven. This capability

prevents excess power consumption caused by a floating bus, thus allowing optimization of power consumption

without the need for external pullup resistors.

TMS320C51 Datasheet(PDF) 29 Page - Texas Instruments

TMS320C51 Datasheet(HTML) 29 Page - Texas Instruments

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