TMS320C51 datasheet(30/87 Pages) TI

30 / 87 page

TMS320C5x, TMS320LC5x

DIGITAL SIGNAL PROCESSORS

SPRS030A – APRIL 1995 – REVISED APRIL 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

external interface

The ’C5x supports a wide range of system interfacing requirements. Program, data, and I/O address spaces

provide interface to memory and I/O, maximizing system throughput. The full 16-bit address and data bus, along

with the PS, DS, and IS space select signals, allow addressing of 64K 16-bit words in each of the three spaces.

I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O

address space using the processor’s external address and data buses in the same manner as memory-mapped

devices.

The ’C5x external parallel interface provides various control signals to facilitate interfacing to the device. The

R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal

provides a timing reference for all external cycles. For convenience, the device also provides the RD and the

WE output signals, which indicate a read and a write cycle, respectively, along with timing information for those

cycles. The availability of these signals minimizes external gating necessary for interfacing external devices to

the ’C5x.

Interface to memory and I/O devices of varying speeds is accomplished by using the READY line. When

transactions are made with slower devices, the ’C5x processor waits until the other device completes its function

and signals the processor via the READY line. Once a ready indication is provided back to the ’C5x from the

external device, execution continues.

The bus request (BR) signal is used in conjunction with the other ’C5x interface signals to arbitrate external

global-memory accesses. Global memory is external data-memory space in which the BR signal is asserted

at the beginning of the access. When an external global-memory device receives the the bus request, the

external device responds by asserting the READY signal after the global memory access is arbitrated and the

global access is completed.

external direct-memory access (DMA) capability

All ’C5x devices with single-access RAM offer a unique feature allowing another processor to read and write

to the ’C5x internal memory. To initiate a read or write operation to the ’C5x single-access RAM, the host or

master processor requests a hold state on the DSP’s external bus. When acknowledged with HOLDA, the host

can request access to the internal bus by pulling the BR signal low. Unlike the hold mode, which allows the

current operation to complete and allows CPU operation to continue (if status bit HM=0), a BR-requested DMA

always halts the operation currently being executed by the CPU. Access to the internal bus always is granted

on the third clock cycle after the BR signal is received. In the PQ package, the IAQ pin also indicates when bus

access has been granted. In the PZ package, this pin is not present so the host is required to wait two clock

cycles after driving the bus request low before beginning DMA transfer.

host port interface (HPI) (TMS320C57S, TMS320LC57, TMS320LC57S only)

The HPI is an 8-bit parallel port used to interface a host processor to the ’C57S /’LC57. The host port is

connected to a 2k word on-chip buffer through a dedicated internal bus. The dedicated bus allows the CPU to

work uninterrupted while the host processor accesses the host port. The HPI memory buffer is a single-access

RAM block which is accessible by both the CPU and the host. The HPI memory also can be used as

general-purpose data or program memory. Both the CPU and the host have access to the HPI control register

(HPIC) and the host can address the HPI memory through the HPI address register (HPIA).

Data transfers of 16-bit words occur as two consecutive bytes with a dedicated pin, HBIL, indicating whether

the high or low byte is being transmitted. Two control pins, HCNTL1 and HCNTL0, control host access to the

HPIA, HPI data (with an optional automatic address increment), or the HPIC. The host can interrupt the

’C57S /’LC57 by writing to HPIC. The ’C57S /’LC57 can interrupt the host with a dedicated HINT pin that the host

acknowledges and clears.

TMS320C51 Datasheet(PDF) 30 Page - Texas Instruments

TMS320C51 Datasheet(HTML) 30 Page - Texas Instruments

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