TMS320C51 datasheet(33/87 Pages) TI

33 / 87 page

TMS320C5x, TMS320LC5x

DIGITAL SIGNAL PROCESSORS

SPRS030A – APRIL 1995 – REVISED APRIL 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

IEEE 1149.1 boundary scan interface

The IEEE 1149.1 boundary-scan interface is used for emulation and test purposes. The IEEE 1149.1 scanning

logic provides the boundary-scan path to and from the interfacing devices. Also, it can be used to test pin-to-pin

continuity as well as to perform operational tests on those peripheral devices that surround the ’C5x. On ’C5x

devices which do not provide boundary-scan capability, the IEEE 1149.1 interface is used for emulation

purposes only. It is interfaced to other internal scanning logic circuitry, which has access to all of the on-chip

resources. Thus, the ’C5x can perform on-board emulation by means of IEEE 1149.1 serial pins and the

emulation-dedicated pins (see IEEE Standard 1149.1 for more details). Table 5 shows IEEE 1149.1 and

boundary-scan functions supported by the ’C5x family of devices.

Table 5. IEEE 1149.1 Interface/Boundary Scan/On-Chip Analysis Block Configurations

on the ’C5x/’LC5x Device Family

DEVICE TYPE

IEEE 1149.1 INTERFACE

BOUNDARY-SCAN CAPABILITY

ON-CHIP ANALYSIS BLOCK

’C50 / ’LC50

Yes

Full

’C51 / ’LC51

Yes

Full

’C52 / ’LC52

Yes

Full

’C53 / ’LC53

Yes

Full

’C53S / ’LC53S

Yes

Reduced

’LC56

Yes

Full

’C57S

Yes

Full

’LC57

Yes

Full

on-chip analysis block

The on-chip analysis block, in conjunction with the ’C5x EVM, provides the capability to perform a variety of

debugging and performance evaluation functions in a target system. The full analysis block provides capability

for message passing by a combination of monitor mode and scan, flexible breakpoint setup based on events,

counting of events, and a PC discontinuity trace buffer. Breakpoints can be triggered based on the following

events: program fetches/reads/writes, EMU0/1 pin activity (used in multiprocessing), data reads/writes, CPU

events (calls, returns, interrupts/traps, branches, pipeline clock), and event-counter overflow. The event counter

is a 16-bit counter which can be used for performance analysis. The event counter can be incremented based

on the occurrence of the following events: CPU clocks (performance monitoring), pipeline advances, instruction

fetches (used to count instructions for an algorithm), branches, calls, returns, interrupts/traps, program

reads/writes, or data reads/writes. The PC discontinuity-trace buffer provides a method to monitor program

counter flow.

These analysis functions are available on all ’C5x devices except the ’C53S and ’LC53S which have a reduced

analysis block (see Table 5). The reduced analysis block provides capability for message passing and

breakpoints based on program fetches/reads/writes and EMU0/1 pin activity.

multiprocessing

The flexibility of the ’C5x allows configurations to satisfy a wide range of system requirements; the device can

be used in a variety of system configurations, including, but not limited to, the following:

D A standalone processor

D A multiprocessor with devices in parallel

D A slave/host multiprocessor with global-memory space

D A peripheral processor interfaced via processor-controlled signals to another device

TMS320C51 Datasheet(PDF) 33 Page - Texas Instruments

TMS320C51 Datasheet(HTML) 33 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87

Datasheet Download

Link URL