TMS320C51 datasheet(76/87 Pages) TI

76 / 87 page

TMS320C5x, TMS320LC5x

DIGITAL SIGNAL PROCESSORS

SPRS030A – APRIL 1995 – REVISED APRIL 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

BUFFERED SERIAL-PORT TRANSMIT TIMING OF INTERNAL FRAME AND INTERNAL CLOCK

(SEE NOTES 9 AND 10)

switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 29)

PARAMETER

MIN

MAX

UNIT

td(CXH-FXH)

Delay time, FSX high after CLKX rising edge

td(CXH-FXL)

Delay time, FSX low after CLKX rising edge

td(CXH-DXV)

Delay time, DX valid after CLKX rising edge

tdis(CXH-DX)

Disable time, DX invalid after CLKX rising edge

tdis(CXH-DX)PCM

Disable time in PCM mode, DX invalid after CLKX rising edge

ten(CXH-DX)PCM

Enable time in PCM mode, DX valid after CLKX rising edge

tc(SCK)

Cycle time, serial-port clock

62H

tf(SCK)

Fall time, serial-port clock

4†

tr(SCK)

Rise time, serial-port clock

4†

tw(SCK)

Pulse duration, serial-port clock low / high

H–4

th(CXH-DXV)

Hold time, DX valid after CLKX rising edge

† Values derived from characterization data and not tested

NOTES:

9. Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending

on the source of FSX, and CLKX timings always are dependent upon the source of CLKX. Specifically, the relationship of FSX to

CLKX is independent of the source of CLKX. External FSX timings are obtained from the “timing requirements over recommended

operating conditions” table listed in the “Buffered Serial-Port Transmit Timing of External Frames” section and internal FSX timings

are obtained from the “switching characteristics over recommended operating conditions” table listed under the “Buffered Serial-Port

Transmit Timing of Internal Frame and Internal Clock” section. Internal CLKX timings are obtained from the “switching characteristics

over recommended operating conditions” table listed under the “Buffered Serial-Port Transmit Timing of Internal Frame and Internal

Clock” section and external CLKX timings are obtained from the “timing requirements over recommended operating conditions” table

in the “Buffered Serial-Port Transmit Timing of External Frames” section.

10. Timings for CLKX and FSX are given with polarity bits (CLKP and FSP) set to 0.

Bit

FSX

CLKX

th(CXH-DXV)

tr(SCK)

tf(SCK)

tw(SCK)

tc(SCK)

td(CXH-FXL)

td(CXH-DXV)

tdis(CXH-DX)

tw(SCK)

8/16

7 /15

td(CXH-FXH)

Figure 29. Buffered Serial-Port Transmit Timing of Internal Clocks and Internal Frames

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