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TMS320C51 Datasheet(PDF) 65 Page - Texas Instruments

Part # TMS320C51
Description  DIGITAL SIGNAL PROCESSORS
PDF  87 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320C51 Datasheet(HTML) 65 Page - Texas Instruments

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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
65
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
INSTRUCTION ACQUISITION (IAQ), INTERRUPT ACKNOWLEDGE (IACK),
EXTERNAL FLAG (XF), AND TOUT (SEE NOTE 6)
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 20)
PARAMETER
’320C5x-40
’320C5x-57
’320LC5x-40
’320LC5x-50
’320C5x-80
’320C5x-100
’320LC5x-80
UNIT
MIN
MAX
MIN
MAX
tsu(AV-IQL)
Setup time, address valid before IAQ low †
H–12‡
H–9‡
ns
th(IQL-AV)
Hold time, address valid after IAQ low
H–10‡
H–7‡
ns
tw(IQL)
Pulse duration, IAQ low
H–10‡
H–7‡
ns
td(CO-TU)
Delay time, CLKOUT1 falling edge to TOUT
–6
6
–6
6
ns
tsu(AV-IKL)
Setup time, address valid before IACK low §
H–12‡
H–9‡
ns
th(IKL-AV)
Hold time, address valid after IACK low
H–10‡
H–7‡
ns
tw(IKL)
Pulse duration, IACK low
H–10‡
H–7‡
ns
tw(TUH)
Pulse duration, TOUT high
2H – 12
2H – 9
ns
td(CO-XFV)
Delay time, XF valid after CLKOUT1
0
12
0
9
ns
† IAQ goes low during an instruction acquisition. It goes low only on the first cycle of the read when wait states are used. The falling edge should
be used to latch the valid address. The AVIS bit in the PMST register must be set to zero for the address to be valid when the instruction being
addressed resides in on-chip memory.
‡ Valid only if the external address reflects the current instruction activity (that is, code is executing on chip with no external bus cycles and AVIS
is on or code is executing off chip)
§ IACK goes low during the fetch of the first word of the interrupt vector. It goes low only on the first cycle of the read when wait states are used.
Address pins A1 – A4 can be decoded at the falling edge to identify the interrupt being acknowledged. The AVIS bit in the PMST register must
be set to zero for the address to be valid when the vectors reside in on-chip memory.
NOTE 6: IAQ pin is not present on 100-pin packages.
IACK pin is not present on 100-pin and 128-pin packages.



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